Abstract: A lifting mechanism comprises a lifting member, a first detection element and a second detection element. The lifting mechanism is applied to a robot, the robot comprises a controller, the controller is electrically connected with the lifting mechanism. The first detection element and the second detection element detect a height of the at least two guide rods, the controller controls the lifting member to move up or down according to the first position signal output by the first detection element and the second position signal output by the second detection element, so that the lifting mechanism can accurately locate the highest ascending position and lowest descending position of the lifting mechanism. A robot is also provided.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements and a color filter layer disposed above the photoelectric conversion elements. The color filter layer has a first color filter segment and a second color filter segment adjacent to the first color filter segment. The first color filter segment and the second color filter segment correspond to different colors. The solid-state image sensor further includes a light-splitting structure disposed in the first color filter segment or the second color filter segment and a grid structure disposed between the first color filter segment and the second color filter segment. The light-splitting structure is separated from the grid structure.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varyies at different heights along the side of the photodiode.

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Abstract: A device includes a gate electrode and a gate dielectric surrounding the gate electrode. The gate electrode surrounds a nanostructure. The nanostructure includes stacked nanosheets. The gate dielectric is formed by a high-k (HK) material. The HK material covers sidewalls of the gate electrode in a direction aligned to adjacent devices. Portions of the HK material are recessed from the sidewalls and refilled by a dielectric material with a dielectric constant less than the HK material and an electrical isolation capability greater than the HK material. Replacing the HK material over the sidewalls of the gate electrode with the dielectric material enhances electrical isolation between the gate electrode with adjacent contacts. Consequently, it can reduce electrical leakage between metal gate (MG) contacts and metal-to-device (MD) contacts in scaled transistors of an integrated circuit (IC).

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: A chip package and method for fabricating the same are provided that includes a power delivery network (PDN) with non-uniform electrical conductance. The electrical conductance through each current path of the PDN may be selected to balance the distribution of current flow across the current paths through the chip package, thus compensating for areas of high and low current draw found in conventional designs.

Abstract: An image sensor includes a sensor unit, a sensing portion disposed within the sensor unit, and an isolation structure corresponding to the sensing portion. The isolation structure includes a first deep trench isolation (DTI) structure surrounding the sensor unit from top view, and a second deep trench isolation structure laterally enclosed by the first deep trench isolation structure. The second deep trench isolation structure is located close to a corner of the sensor unit defined by the first deep trench isolation structure. The second deep trench isolation structure is asymmetrical with respect to a horizontal middle line or a vertical middle line within the sensor unit.

Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface, a first sidewall of the source epitaxial structure, and a second sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.

Abstract: A device includes a stack of semiconductor nanostructures, a gate structure wrapping around the semiconductor nanostructures, a source/drain region abutting the gate structure and the stack, a contact structure on the source/drain region, a backside dielectric layer under the stack, and a via structure extending from the contact structure to a top surface of the backside dielectric layer.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.

Abstract: A device to control the charging or cessation of charging a robot battery is installed in a robot. The device for autonomous charging battery includes the robot battery, a charging mechanism, a relay, a first controller, and a second controller. The relay is electrically connected with the charging mechanism and the first controller, the battery is electrically connected with the charging mechanism, the second controller communicates with the first controller, and the charging mechanism is used for electrically connecting an external charging device. The second controller is configured to receive the robot control command and output the relay control command to the first controller based on the robot control command. The first controller is configured to switch the relay on or off based on the control command to control charging or cessation of charging. A method of autonomous charging battery is also provided.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: A shielding housing structure of an electric connector includes an insulating body including a first terminal slot for insertion of a first terminal set, a second terminal slot for insertion of a second terminal set, a socket for insertion of a preset board; a shielding housing having an accommodation space assembled with a top side of the insulating body, and top holes and lateral holes formed thereon, and an insertion hole formed on upper edges of the lateral holes; and a movable cover having a top covering plate having top openings, and a side covering plate having lateral openings. The top covering plate is plugged into the insertion hole, and can be slid to a first position to form thermal convection ventilation holes on the shielding housing structure, or the top covering plate can be slid to a second position to form an enclosing status of the shielding housing.

Abstract: A method for compensating driving parameters for a display and a circuit system for the same are provided. The method is performed in a backlight control circuit of a backlight module and a display driving circuit of a display panel of a display. A compensation parameter table is introduced. The compensation parameter table records compensation parameters applied to the backlight module and the display panel under different brightness and chrominance. When the backlight module and the display panel are in operation, the compensation parameters can be obtained by querying the compensation parameter table according to voltage and current values applied to the circuit system of the display. The backlight control circuit then outputs driving signals to each LED driving circuit according to the compensation parameters for each region. The display driving circuit outputs driving signals to display elements of the display panel according to the compensation parameters.