Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A plasma-assisted annealing system includes a high temperature furnace, a plasma-induced dissociator and a connecting duct. The plasma-induced dissociator is provided to dissociate a working gas and exhaust the dissociated working gas from its working gas outlet. Both ends of the connecting duct are connected to the working gas outlet of the plasma-induced dissociator and a gas inlet of the high temperature furnace, respectively. The working gas dissociated in the plasma-induced dissociator is introduced into the high temperature furnace via the connecting duct.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: A touch display device is provided in this disclosure. The touch display device includes a substrate, a first conductive layer, a second conductive layer, a stacked structure, an inorganic light emitting unit, and a touch sensing circuit. The first conductive layer is disposed on the substrate. The first conductive layer includes a gate electrode. The second conductive layer is disposed on the first conductive layer. The second conductive layer includes a source electrode and a drain electrode. The stacked structure is disposed on the substrate. The stacked structure includes a conductive channel and a sensing electrode. The inorganic light emitting unit is disposed on the stacked structure. The inorganic light emitting unit is electrically connected with the drain electrode via the conductive channel. The touch sensing circuit is electrically connected with the sensing electrode.

Abstract: An electrostatic sensing system configured to sense an electrostatic information of a fluid inside a fluid distribution component and including an electrostatic sensing assembly, a signal amplifier and an analog-to-digital converter. The electrostatic sensing assembly includes a sensing component, and a shield. The sensing component is configured to be disposed at the fluid distribution component. The sensing component is disposed through the fluid distribution component so as to be partially located in the fluid distribution component. The shield surrounds a part of the sensing component that is located in the fluid distribution component. At least part of the shield is located on an upstream side of the sensing component. The signal amplifier is electrically connected to the sensing component. The analog-to-digital converter is electrically connected to the signal amplifier. The shield has an opening spaced apart from the sensing component.

Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Abstract: A level shifter includes a cross-coupled transistor pair, first through third cascode transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first cascode transistor pair is controlled by a first reference voltage. The second cascode transistor pair is controlled by a pair of differential control voltages. The third cascode transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second cascode transistor pair.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.

Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.

Abstract: A semiconductor device includes nanostructures vertically arranged and spaced apart from one another along a first direction. The semiconductor device also includes a dielectric fin structure of a dielectric material of uniform composition and an isolation structure on opposite sides of the nanostructures. Moreover, the semiconductor device also includes a gate structure wrapping around the nanostructures. The gate structure extends between the nanostructure and the dielectric fin structure, and extends between the nanostructures and the isolation structure. Furthermore, the nanostructures are spaced apart from the dielectric fin structure along a second direction perpendicular to the first direction by a first distance, and from the isolation structure along the second direction by a second distance, where the first distance is greater than the second distance. Additionally, the gate structure interfaces with the dielectric fin structure on a surface extending perpendicular to the first direction.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a nonconductive support element. The first radiation element has a feeding point. The second radiation element is coupled to the first radiation element. The third radiation element is coupled to a ground voltage and adjacent to the first radiation element. The fourth radiation element is coupled to the first radiation element. The fifth radiation element is coupled to the ground voltage and adjacent to the second radiation element. The first radiation element, the second radiation element, the third radiation element, and the fourth radiation element are at least partially surrounded by the fifth radiation element. The first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element are disposed on the nonconductive support element.

Abstract: According to embodiments of the present disclosure, a method and a chip for cyclic code encoding, a circuit component, and an electronic device are provided. The method includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; generating the (N?K) parity symbols based on the first parity sequence and the second parity sequence.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a feeding point. The second radiation element is coupled to the first radiation element. The third radiation element is coupled to a first grounding point. The third radiation element is further coupled through the fourth radiation element to a second grounding point. The fifth radiation element is coupled to the third radiation element and the fourth radiation element. The fifth radiation element is adjacent to the second radiation element. The first radiation element and the second radiation element are at least partially surrounded by the third radiation element, the fourth radiation element, and the fifth radiation element.

Abstract: A semiconductor device includes an electronic device, a guard trace and a first trace. The guard trace is connecting to a ground layer through a first ground via. The first trace is disposed adjacent to the electronic device and the guard trace and includes a first segment. A phase or a direction of a first current signal conducted on the first trace is changed in the first segment. The electronic device and the first trace are disposed at different sides of the guard trace and the first ground via is beside the first segment.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.