Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.

Abstract: An image sensor includes groups of sensor units, and a color filter layer having color units that disposed within the groups of sensor units, respectively. The color units of the color filter layer include a yellow color unit or a white color unit. The image sensor further includes a dielectric structure disposed on the color filter layer, and a meta surface disposed on the dielectric structure.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a nanostructure, an isolation structure, an isolation fin, and a gate stack. The method includes turning the substrate upside down and removing the base to expose the isolation structure. The method includes partially removing the isolation structure to form a first trench in the isolation structure. The first trench exposes a portion of the isolation fin. The method includes removing the portion of the isolation fin through the first trench to form a second trench in the gate stack. The method includes partially removing the gate stack through the first trench and the second trench. The second trench passes through the gate stack and divides the gate stack into a first part and a second part.

Abstract: A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a circuit layer over the substrate. The semiconductor device further includes a test line electrically connected to the circuit layer. The semiconductor device further includes a capacitor on the substrate. The capacitor includes a first conductor, wherein the first conductor is on a portion of the substrate exposed by the circuit layer. The capacitor further includes an insulator surrounding the first conductor.

Abstract: An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Abstract: In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.

Abstract: A method provides a structure having a fin oriented lengthwise and widthwise along first and second directions respectively, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin. The method includes forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature; removing the first portion of the fin, resulting in a first trench; forming a first dielectric feature in the first trench; and removing the second portion of the fin to form a second trench. The first dielectric feature and the isolation structure form first and second sidewalls of the second trench respectively. The method includes laterally etching the second sidewalls, thereby expanding the second trench along the second direction and forming a via structure in the expanded second trench.

Abstract: An operating method of an under-display camera system includes: providing a raw data by a pixel array; generating, by a plurality of color filters respectively disposed on a plurality of first photodiodes of the pixel array, a color information in accordance with the raw data; generating, by a plurality of first narrowband filters respectively disposed on a plurality of second photodiodes of the pixel array, a first narrowband information in accordance with the raw data, wherein a spectrum linewidth of the plurality of first narrowband filters is in a range from 5 nm to 70 nm; reconstructing an edge information from the first narrowband information based on one of a plurality of diffraction patterns provided by a database unit of a point spread function; and obtaining an image by combining the edge information with the color information.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a dummy fin structure, a mask layer, a first source/drain contact, and an isolation plug. The gate structure crosses the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The dummy fin structure is in contact with the first source/drain epitaxial structure. The mask layer is over the dummy fin structure. The first source/drain contact is over and electrically connected to the first source/drain epitaxial structure. The isolation plug is over the mask layer and in contact with the first source/drain contact. The isolation plug is directly over the first source/drain contact and the mask layer.

Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

Abstract: An operating method of an under-display camera system includes: providing a raw data by a pixel array; generating, by a plurality of color filters respectively disposed on a plurality of first photodiodes of the pixel array, a color information in accordance with the raw data; generating, by a plurality of first narrowband filters respectively disposed on a plurality of second photodiodes of the pixel array, a first narrowband information in accordance with the raw data, wherein a spectrum linewidth of the plurality of first narrowband filters is in a range from 5 nm to 70 nm; reconstructing an edge information from the first narrowband information based on one of a plurality of diffraction patterns provided by a database unit of a point spread function; and obtaining an image by combining the edge information with the color information.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.