Patents by Inventor Chun-Yuan Wu
Chun-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476367Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: GrantFiled: August 23, 2021Date of Patent: October 18, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
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Publication number: 20210384359Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: United Microelectronics Corp.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
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Patent number: 11133418Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: GrantFiled: May 15, 2019Date of Patent: September 28, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
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Patent number: 10763260Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.Type: GrantFiled: December 11, 2018Date of Patent: September 1, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
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Patent number: 10573649Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.Type: GrantFiled: February 17, 2016Date of Patent: February 25, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Chia-Hsun Tseng, Cheng-Tzung Tsai, Chun-Yuan Wu
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Patent number: 10497797Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.Type: GrantFiled: November 16, 2015Date of Patent: December 3, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Kun-Hsin Chen, Tien-I Wu, Yu-Ru Yang, Huai-Tzu Chiang
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Patent number: 10446447Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.Type: GrantFiled: July 16, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Fan Li, I-Cheng Hu, Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin, Chun-Yuan Wu
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Patent number: 10439023Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: GrantFiled: July 19, 2018Date of Patent: October 8, 2019Assignee: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Publication number: 20190267492Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Applicant: United Microelectronics Corp.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
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Patent number: 10381380Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element.Type: GrantFiled: April 8, 2018Date of Patent: August 13, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Fu Hsu, Chun-Yuan Wu
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Patent number: 10381228Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.Type: GrantFiled: February 25, 2015Date of Patent: August 13, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
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Publication number: 20190229053Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.Type: ApplicationFiled: January 22, 2018Publication date: July 25, 2019Inventors: Ya-Jyuan Hung, Ai-Sen Liu, Bin-Siang Tsai, Chin-Fu Lin, Chun-Yuan Wu
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Patent number: 10347716Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.Type: GrantFiled: October 18, 2017Date of Patent: July 9, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
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Patent number: 10340391Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: GrantFiled: June 29, 2017Date of Patent: July 2, 2019Assignee: United Microelectronics Corp.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
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Publication number: 20190115352Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.Type: ApplicationFiled: December 11, 2018Publication date: April 18, 2019Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
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Patent number: 10236294Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.Type: GrantFiled: December 27, 2017Date of Patent: March 19, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
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Patent number: 10177231Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: GrantFiled: October 30, 2017Date of Patent: January 8, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Publication number: 20190006519Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Applicant: United Microelectronics Corp.Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
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Fabricating method of a semiconductor device with a high-K dielectric layer having a U-shape profile
Patent number: 10141193Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.Type: GrantFiled: November 24, 2015Date of Patent: November 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai -
Publication number: 20180331044Abstract: A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure.Type: ApplicationFiled: June 15, 2017Publication date: November 15, 2018Applicant: United Microelectronics Corp.Inventors: Yi-Yu Wu, Chun-Yuan Wu, Chih-Chien Liu, Bin-Siang Tsai