Patents by Inventor Chun-Yuan Wu

Chun-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170098710
    Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Publication number: 20170098692
    Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
    Type: Application
    Filed: November 9, 2015
    Publication date: April 6, 2017
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
  • Publication number: 20170092771
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.
    Type: Application
    Filed: November 27, 2015
    Publication date: March 30, 2017
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu, Xu Yang Shen, ZHIBIAO ZHOU, Qinggang Xing
  • Patent number: 9608126
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu, Xu Yang Shen, Zhibiao Zhou, Qinggang Xing
  • Patent number: 9590041
    Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.
    Type: Grant
    Filed: December 6, 2015
    Date of Patent: March 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ru Yang, Huai-Tzu Chiang, Sheng-Hao Lin, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
  • Publication number: 20170062484
    Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.
    Type: Application
    Filed: October 1, 2015
    Publication date: March 2, 2017
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • Publication number: 20170040415
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.
    Type: Application
    Filed: August 30, 2015
    Publication date: February 9, 2017
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Chun-Yuan Wu
  • Patent number: 9559189
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: January 31, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Patent number: 9543448
    Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: November 1, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • Patent number: 9466727
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, a plug, a hydrogen blocking layer and an oxide semiconductor (OS) structure. The MOS transistor is disposed on the substrate, and the plug is disposed on the MOS transistor to electrically connect thereto. The hydrogen blocking layer is disposed only on sidewalls of the plug, wherein the hydrogen blocking layer includes a high-k dielectric layer. The OS structure is disposed on the substrate, wherein the OS structure includes an oxide semiconductor layer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • Patent number: 9461150
    Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 4, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Hsin-Kuo Hsu, Chih-Chien Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 9455351
    Abstract: An oxide semiconductor field effect transistor (OS FET) device includes a first dielectric layer formed on a substrate, an oxide semiconductor (OS) island formed on the first dielectric layer, a first gate electrode formed on the OS island, a gate dielectric layer formed in between the first gate electrode and the OS island, a patterned hard mask layer formed on a top surface of the first gate electrode, an etch stop layer covering a top surface of the patterned hard mask layer and sidewalls of the first gate electrode, and a source electrode and a drain electrode formed on the OS island. At least one of the source electrode and the drain electrode partially overlaps the etching stop layer on the sidewalls of the first gate electrode.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin, Chun-Yuan Wu
  • Patent number: 9431441
    Abstract: A back side illumination image sensor pixel structure includes a substrate having a front side and a back side opposite to the front side, a sensing device formed in the substrate to receive an incident light through the back side of the substrate, two oxide-semiconductor field effect transistor (OS FET) devices formed on the front side of the substrate, and a capacitor formed on the front side of the substrate. The two OS FET devices are directly stacked on the sensing device and the capacitor is directly stacked on the OS FET devices. The two OS FET devices overlap the sensing device, and the capacitor overlaps both of the OS FET devices and the sensing device.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: August 30, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin, Chun-Yuan Wu, Chia-Fu Hsu
  • Patent number: 9412590
    Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • Patent number: 9401429
    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a suspended part. The gate surrounds the suspended part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a suspended part in the corresponding top part, thereby forming the suspended part over a through hole. A gate is formed to surround the suspended part.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: July 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • Publication number: 20160211144
    Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.
    Type: Application
    Filed: February 25, 2015
    Publication date: July 21, 2016
    Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20160148816
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 26, 2016
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu
  • Patent number: 9349873
    Abstract: Provided is an oxide semiconductor device. A source, a drain, and a first gate are buried in a first dielectric layer, and the first gate is located between the source and the drain. A first barrier layer is located on the first dielectric layer, partially overlaps the source and the drain and overlaps the first gate. The first barrier layer includes a first opening and a second opening respectively corresponds to the source and the drain. An oxide semiconductor layer covers the first barrier layer and fills in the first opening and the second opening. A second barrier layer is located on the oxide semiconductor layer. A second gate is located on the second barrier layer and overlaps with the source, the drain, and the first gate.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 24, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Zhi-Biao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin, Chun-Yuan Wu
  • Publication number: 20160111527
    Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Chin-Cheng Chien, Hsin-Kuo Hsu, Chih-Chien Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 9318567
    Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu