Patents by Inventor Chun-Yuan Wu

Chun-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure with different fins of FinFETs
    Patent number: 9184292
    Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Semiconductor device having strained fin structure and method of making the same
    Patent number: 9184100
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 10, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chih-Chien Liu, Chin-Cheng Chien, Chin-Fu Lin
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20150303283
    Abstract: A method for manufacturing a semiconductor device includes the following steps. A substrate including at least a fin layer and a plurality of gate electrodes is provided. A tilt and twist ion implantation is performed to form a plurality of doped regions in the fin layer. An etching process is performed to remove the doped regions to form a plurality of recesses in the fin layer.
    Type: Application
    Filed: May 16, 2014
    Publication date: October 22, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Ted Ming-Lang Guo
  • Metal gate structure and manufacturing method thereof
    Patent number: 9166020
    Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: October 20, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chan-Lon Yang, Chi-Mao Hsu, Chun-Yuan Wu, Tzyy-Ming Cheng, Shih-Fang Tzou, Chin-Fu Lin, Hsin-Fu Huang, Min-Chuan Tsai
  • Multigate field effect transistor and process thereof
    Patent number: 9159831
    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chun-Yuan Wu, Chin-Fu Lin, Chin-Cheng Chien, Chia-Lin Hsu
  • SEMICONDUCTOR PROCESS FOR MODIFYING SHAPE OF RECESS
    Publication number: 20150263170
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 17, 2015
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER
    Publication number: 20150255307
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 10, 2015
    Inventors: Kun-Hsien LIN, Hsin-Fu HUANG, Chi-Mao HSU, Chin-Fu LIN, Chun-Yuan WU
  • METHOD OF FORMING INTER-LEVEL DIELECTRIC LAYER
    Publication number: 20150206803
    Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.
    Type: Application
    Filed: January 19, 2014
    Publication date: July 23, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Tzu-Chin Wu, Jei-Ming Chen, Yu-Ren Wang, Chun-Yuan Wu, Chin-Fu Lin
  • Manufacturing process of gate stack structure with etch stop layer
    Patent number: 9087782
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 21, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Semiconductor process for modifying shape of recess
    Patent number: 9076652
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: July 7, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • Method of fabricating semiconductor device
    Patent number: 9018087
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu
  • Method of Manufacturing Semiconductor Device Having Metal Gate
    Publication number: 20150079777
    Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ted Ming-Lang Guo, Chiu-Hsien Yeh, Chin-Cheng Chien, Chun-Yuan Wu
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20150064896
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu
  • Method of forming opening on semiconductor substrate
    Patent number: 8962486
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • Semiconductor device
    Patent number: 8921944
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu
  • METHOD OF FABRICATING SEMICONDUCTOR PATTERNS
    Publication number: 20140370701
    Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu, Chin-Cheng Chien, Chun-Yuan Wu
  • SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    Publication number: 20140367779
    Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • SEMICONDUCTOR PROCESS
    Publication number: 20140349467
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Application
    Filed: May 27, 2013
    Publication date: November 27, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • SEMICONDUCTOR STRUCTURE WITH DIFFERENT FINS OF FINFETS
    Publication number: 20140332824
    Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Strained silicon channel semiconductor structure
    Patent number: 8853740
    Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ted Ming-Lang Guo, Chin-I Liao, Chin-Cheng Chien, Shu-Yen Chan, Chun-Yuan Wu