Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, an active element, a driving circuit element, a first connection circuit, a second connection circuit and a conductive connector. The substrate has a first surface and a second surface opposite to the first surface. The active element is disposed on the first surface. The driving circuit element is disposed on the second surface and is overlapped with the active element. The first connection circuit is disposed on the first surface and is connected to the active element. The second connection circuit is disposed on the second surface and is connected to the driving circuit element. The conductive connector penetrates through the substrate and two ends of the conductive connector are electrically connected to the first connection circuit and the second connection circuit, respectively.

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: An audio parameter optimizing method and a computing apparatus related to audio parameters. In the method, sound features of multiple sound signals are obtained. A wide dynamic range compression (WDRC) parameter corresponding to each of the sound signals is determined. Multiple data sets including the sound features and the corresponding WDRC parameters of the sound signals are created. The data sets are used to train a neural network, so as to generate a parameter inference model. The parameter inference model is configured to determine the WDRC parameter of a to-be-evaluated signal. Accordingly, a proper parameter could be provided.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.

Abstract: An electronic device having a first area and a second area adjacent to the first area is provided, which includes a flexible substrate, a first conductive layer disposed on the flexible substrate and in the first area and the second area, a semiconductor disposed on the flexible substrate and electrically connected to the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic layer disposed on the first conductive layer and in the first area and the second area. The second conductive layer has a first portion and a second portion are respectively contacted the first conductive layer in the first area. In a cross-sectional view, a first portion of the organic layer is directly contacted the first conductive layer and the second conductive layer and disposed between the first portion and the second portion of the second conductive layer.

Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) formed within in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

Abstract: A semiconductor structure includes a circuit with a redistribution layer (RDL) formed over the circuit. The redistribution layer comprises a plurality of metal layers. An inductor is formed in a topmost metal layer, and the circuit is located directly under the inductor. An under bump metallization (UBM) layer formed on the topmost metal layer and a conductive connector formed on the UBM layer.

Abstract: A method for training a segmentation model is provided. The method includes using first training images to train a segmentation model. The method includes using second training images to train an image generator. The method includes inputting real images into the segmentation model to generate predicted annotation images. The method includes inputting the predicted annotation images into the image generator to generate fake images. The method includes updating the segmentation model and the image generator according to a loss caused by differences between the real images and the fake images.

Abstract: The present disclosure provides an electronic device, which includes an encapsulant, an electronic component, an antenna structure, and a first conductive element. The electronic component is disposed in the encapsulant. The antenna structure has an antenna pattern exposed to air and facing the encapsulant, and a first supporting element separating the antenna pattern from the encapsulant. At least a portion of the first conductive element is within the encapsulant, and electrically connects the antenna pattern to the electronic component by the first supporting element.

Abstract: A method includes forming a gate structure on a semiconductor substrate; depositing a carbon-containing seal layer over the gate structure; depositing a nitrogen-containing seal layer over the carbon-containing seal layer; introducing an oxygen-containing precursor on the nitrogen-containing seal layer; heating the substrate to dissociate the oxygen-containing precursor into an oxygen radical to dope into the nitrogen-containing seal layer; after heating the substrate, etching the nitrogen-containing seal layer and the carbon-containing seal layer, such that a remainder of the nitrogen-containing seal layer and the carbon-containing seal layer remains on a sidewall of the gate structure as a gate spacer.

Abstract: A light-emitting diode includes an epitaxial structure, a first electrical connection structure, a second electrical connection structure, a first insulation layer, and a second insulation layer. The epitaxial structure has a first surface, a second surface opposite to the first surface, and a side boundary surface formed between the first surface and the second surface, and includes a first type semiconductor layer, an active layer and a second type semiconductor layer that are sequentially arranged. The epitaxial structure is formed with at least one recess on the second surface. The at least one recess is formed near a periphery of the side boundary surface. The first electrical connection structure has a protrusion extending through the at least one recess, and electrically connected to the first type semiconductor layer. At least a portion of the side boundary surface positioned above the at least one recess has a roughened surface.

Abstract: A planar transparent antenna structure is provided. The planar transparent antenna structure includes a dielectric substrate, a radiation patch conductive layer, a parasitic patch conductive layer and a ground conductive layer. The radiation patch conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer is a ring structure. The parasitic patch conductive layer is disposed on the dielectric substrate. The ground conductive layer is disposed on the dielectric substrate. The radiation patch conductive layer, the parasitic patch conductive layer and the ground conductive layer are composed of a plurality of wires interconnected and connected with each other and are light-transmissive.