Abstract: A multi-radar based detection device and detection method for a target object are provided. In the detection method, a first detection result corresponding to a first detection space and a second detection result corresponding to a second detection space are received. The first detection space entering a first status is determined in response to the first detection result indicating that the target object in the first detection space moves to an overlapping area between the first detection space and the second detection space. First information is output in response to determining that the first detection space enters the first status. The second detection space entering a second status is determined in response to the second detection result indicating that the target object not in the second detection space appears in the overlapping area. Second information is output in response to determining that the second detection space enters the second status.

Abstract: The present invention discloses a photocell device with a responsivity amplifying structure, comprising: a partially reflective filter layer that transmits light within a specific wavelength range and reflects other wavelengths; a gain layer that interacts with photons to alter their wavelength; and an optoelectronic reaction layer. The gain layer is positioned between the partially reflective filter layer and the reaction layer. Photons interacting with the gain layer either enter the reaction layer for conversion or are reflected back for interacting with the gain layer again and then entering the reaction layer for conversion. In another embodiment, an additional reflective filter is placed between the gain layer and the optoelectronic reaction layer.

Abstract: Provides a flexible copper clad laminate, which includes a polyimide substrate; a nickel-copper alloy layer; and a copper layer. The nickel-copper alloy layer is formed on at least one side of the polyimide substrate by electroless plating and comprises at least nickel, copper and phosphorus. A content of the copper is more than 30 wt % of the nickel-copper alloy layer, a content of the phosphorus is less than 5 wt % of the nickel-copper alloy layer, and a corrosion potential of the nickel-copper alloy layer in a 0.02 vol % sulfuric acid solution is greater than ?20 mV. The copper layer is formed on a side of the nickel-copper alloy layer away from the polyimide substrate and combined with the nickel-copper alloy layer to form a metal conductive layer. In addition, the aforementioned flexible copper clad laminate has electrochemical corrosion resistance and sufficient peel strength, facilitating the production of flexible printed circuit boards.

Abstract: A medical image analysis system comprises: a database for storing a first medical image data indicating a target medical image; and a server for accessing the database. The server includes: a first analysis module for generating a first determination data according to the first medical image data; a second analysis module for generating a second determination data according to the first medical image data; and an ensemble module communicatively connected with the first and second analysis modules and generating a third determination data according to the first and second determination data. The first and second determination data each indicate whether the target medical image includes a cancerous tissue image or indicate a chance of the target medical image including a cancerous tissue image. The third determination data indicates whether the target medical image includes a cancerous tissue image.

Abstract: A LED includes: a metal substrate including a first metal layer; a semiconductor layer sequence disposed on the metal substrate, where the semiconductor layer sequence includes a first semiconductor layer, a second semiconductor layer and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first electrode, electrically connected to the first semiconductor layer; and a second electrode, electrically connected to the second semiconductor layer. A side of the metal substrate facing away the semiconductor layer sequence defines a groove, a second metal layer is disposed in the groove, the metal substrate includes a groove edge which is protruded, and the groove edge is no more than 0.5 ?m higher than the second metal layer, enhancing the reliability of the LED in the packaged bonding product.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Abstract: An example foldable mobile computing device includes a first side including a first power storage device coupled to a first regulator. The device includes a second side including a second power storage device coupled to a second regulator and connected in parallel with the first power storage device. The second side is configured to articulate relative to the first side about a hinge. The device includes processing circuitry configured to determine a power storage capacity of the first power storage device and to determine a power storage capacity of the second power storage device. The device is also configured to adjust, based on the power storage capacity of the first power storage device and the power storage capacity of the second power storage device, at least one of an impedance of the first regulator or an impedance of the second regulator.

Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

Abstract: A display panel including a substrate, scan lines, data lines, pixel structures, and a light shielding pattern layer is provided. The substrate is provided with a display area. The scan lines and the data lines are disposed on the substrate, and intersect with each other. The pixel structures are disposed in the display area, and each includes a display transistor and a pixel electrode. The display transistor includes a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is disposed between the substrate and the first semiconductor pattern, and is electrically connected to one of the scan lines. The first source electrode is electrically connected to one of the data lines. The pixel electrode is electrically connected to the first drain electrode of the display transistor. The light shielding pattern layer is disposed between the first gate electrode and the substrate, and has a first opening overlapping the first gate electrode.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: A chemical mechanical polishing apparatus includes a platen to hold a polishing pad, a carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, a polishing liquid dispenser having a polishing liquid port positioned over the platen to deliver polishing liquid onto the polishing pad, a temperature control system including coolant liquid fluid reservoirs for containing coolant fluids, a thermal controller configured to control the temperature of the coolant fluid within the coolant fluid reservoirs, and a first dispenser having openings in fluid connection with the coolant fluid reservoirs, the openings positioned configured to spray an aerosolized coolant liquid directly onto the polishing pad, and a second dispenser having a coolant port in fluid connection with the coolant fluid reservoirs, the coolant port positioned over the platen and configured to flow a stream of coolant liquid directly onto the polishing pad.

Abstract: A lithography method includes the steps which are mentioned below. A photoresist layer is formed over a substrate. The photoresist layer is exposed. The photoresist layer is developed. A vacuum treatment is performed to the photoresist layer. The substrate is etched by using the photoresist layer as an etch mask.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.

Abstract: A planting column includes a hollow pillar including upper and lower end portions, a body portion located between the upper and lower end portions, and an accommodating chamber located in the body portion. The upper end portion includes a top opening communicating with the accommodating chamber. The body portion includes through holes communicating the accommodating chamber with the outside of the hollow pillar. The lower end portion includes an inner surface opposite to the top opening, an outer surface, and at least one through hole penetrating through the inner and outer surfaces and communicating the accommodating chamber with the outside of the hollow pillar. The planting column is adapted for a climbing plant to grow and climb thereon, and helps for ramet of the climbing plant. The planting column is insertable in the soil, and helps for improving the soil's water permeability and breathability.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: An optical structure is provided. The optical structure includes a substrate, a light-emitting element, a glue layer, and a light-adjusting element. The light-emitting element is disposed on the substrate. The glue layer covers the light-emitting element. The light-adjusting element is disposed on the glue layer. Moreover, the refractive index of the glue layer is different from the refractive index of the light-adjusting element.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.