Abstract: A lithography method includes the steps which are mentioned below. A photoresist layer is formed over a substrate. The photoresist layer is exposed. The photoresist layer is developed. A vacuum treatment is performed to the photoresist layer. The substrate is etched by using the photoresist layer as an etch mask.

Abstract: An optical structure is provided. The optical structure includes a substrate, a light-emitting element, a glue layer, and a light-adjusting element. The light-emitting element is disposed on the substrate. The glue layer covers the light-emitting element. The light-adjusting element is disposed on the glue layer. Moreover, the refractive index of the glue layer is different from the refractive index of the light-adjusting element.

Abstract: A chemical mechanical polishing apparatus includes a platen to hold a polishing pad, a carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, a polishing liquid dispenser having a polishing liquid port positioned over the platen to deliver polishing liquid onto the polishing pad, a temperature control system including coolant liquid fluid reservoirs for containing coolant fluids, a thermal controller configured to control the temperature of the coolant fluid within the coolant fluid reservoirs, and a first dispenser having openings in fluid connection with the coolant fluid reservoirs, the openings positioned configured to spray an aerosolized coolant liquid directly onto the polishing pad, and a second dispenser having a coolant port in fluid connection with the coolant fluid reservoirs, the coolant port positioned over the platen and configured to flow a stream of coolant liquid directly onto the polishing pad.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.

Abstract: A planting column includes a hollow pillar including upper and lower end portions, a body portion located between the upper and lower end portions, and an accommodating chamber located in the body portion. The upper end portion includes a top opening communicating with the accommodating chamber. The body portion includes through holes communicating the accommodating chamber with the outside of the hollow pillar. The lower end portion includes an inner surface opposite to the top opening, an outer surface, and at least one through hole penetrating through the inner and outer surfaces and communicating the accommodating chamber with the outside of the hollow pillar. The planting column is adapted for a climbing plant to grow and climb thereon, and helps for ramet of the climbing plant. The planting column is insertable in the soil, and helps for improving the soil's water permeability and breathability.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

Abstract: An antenna device based on a transparent substrate and a method of configuring an antenna device are provided. The antenna device includes a transparent substrate, a first dielectric layer, and an antenna. The transparent substrate includes a first surface and a second surface opposite to the first surface. The first dielectric layer includes a third surface and a fourth surface opposite to the third surface, wherein the first dielectric layer is in contact with the first surface via the third surface to be disposed on the transparent substrate, wherein a permittivity of the first dielectric layer is less than a permittivity of the transparent substrate. The antenna includes a radiation part, wherein the radiation part is disposed on one of the second surface and the fourth surface.

Abstract: The invention is related to contact lenses that not only comprise the much desired water gradient structural configurations, but also have a minimized uptakes of polycationic antimicrobials and a long-lasting surface hydrophilicity and wettability even after going through a 30-days lens care regime. Because of the water gradient structural configuration and a relatively-thick, extremely-soft and water-rich hydrogel surface layer, a contact lens of the invention can provide superior wearing comfort. Further, a contact lens of the invention is compatible with multipurpose lens care solutions present in the market and can endure the harsh lens care handling conditions (e.g., digital rubbings, accidental inversion of contact lenses, etc.) encountered in a daily lens care regime. As such, they are suitable to be used as weekly- or monthly-disposable water gradient contact lenses.

Abstract: A glass composition includes, based on 100 wt % of the glass composition, silicon dioxide present in an amount ranging from 45 wt % to 61 wt %, aluminum oxide present in an amount (A) ranging from 15 wt % to 22 wt %, calcium oxide present in an amount (C) ranging from 0.1 wt % to 6 wt %, magnesium oxide present in an amount (M) of greater than 0 wt % and lower than 2 wt %, zinc oxide present in an amount of greater than 0 wt % and lower than 8 wt %, copper oxide present in an amount of greater than 0 wt % and lower than 7 wt %, and boron oxide present in an amount of greater than 6 wt % and lower than 18 wt %. A glass fiber including the glass composition, and an electronic product including the glass fiber are also provided.

Abstract: A method can include determining which computing units in a computing-in-memory (CIM) macro are to be turned off, the CIM macro including an array of the computing units with X rows and Y columns, the X rows of computing units being organized into N row-groups, each row-group including multiple rows of computing units, the Y columns of computing units being organized into M column-groups, each column-group including multiple columns of computing units, based on the determination of which computing units in the CIM macro are to be turned off, turning off at least one row-group or column-group of computing units, each row-group and column-group of computing units being separately controllable to be turned off, and performing a computation based on kernel weights and activations of a neural network stored in the active computing units in the CIM macro that are not turned off.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: Small interfering RNAs (siRNA) having specific modification patterns to improve interference efficiencies thereof. The modification patterns each comprises a combination of 2?-O methyl modification, 2?-O-fluoro-modification, and phosphorothioate (PS) bonds at defined positions in the sense strand and anti-sense strand of each siRNA, and optionally 5? phosphate modifications.

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: Some embodiments disclosed herein are directed to battery cells with battery stacks having different tab lengths. Some embodiments may include a first battery stack that includes a first plurality of tabs extending from the first battery stack, and a second battery stack adjacent to the first battery stack that includes a second plurality of tabs extending from the second battery stack, where the second plurality of tabs are shorter than the first plurality of tabs. A weld plate may be welded to the first plurality of tabs and the second plurality of tabs without trimming the first plurality of tabs. Other embodiments may be disclosed or claimed.

Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.