Patents by Inventor Chung Chang

Chung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11991859
    Abstract: An apparatus may include a heat pipe with a first portion residing in a first plane, a second portion residing in the first plane and a third portion positioned between the first portion and the second portion, the third portion residing in a second plane spaced-apart from the first plane. The apparatus further includes a base plate including an opening and a clip plate having a first region, a second region and a third region positioned between the first and the second regions. The third portion of the heat pipe is positioned within the opening, and the clip plate is coupled to the base plate such that i) the third region of the clip plate is in superimposition with the third portion of the heat pipe and ii) third region of the clip plate resides in the first plane.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: May 21, 2024
    Assignee: Dell Products L.P.
    Inventors: Chin-Chung Wu, Chun-Han Lin, Che-Jung Chang, Yueh Ching Lu
  • Publication number: 20240160826
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 16, 2024
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Publication number: 20240162618
    Abstract: An antenna structure includes a metal mechanism element, a ground element, a feeding radiation element, a first radiation element, a second radiation element, a parasitic radiation element, a tuning circuit, and a nonconductive support element. The metal mechanism element has a slot. The metal mechanism element includes a first grounding portion and a second grounding portion. The slot is positioned between the first grounding portion and the second grounding portion. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The parasitic radiation element is coupled to the ground element. The parasitic radiation element is adjacent to the first radiation element and the second radiation element. The tuning circuit is coupled between the first grounding portion and the second grounding portion of the metal mechanism element.
    Type: Application
    Filed: October 18, 2023
    Publication date: May 16, 2024
    Inventors: Wei-Chung CHANG, Shang-Ching TSENG
  • Patent number: 11982944
    Abstract: A method of lithography process is provided. The method includes forming a conductive layer over a reticle. The method includes applying ionized particles to the reticle by a discharging device. The method includes forming a photoresist layer over a semiconductor substrate. The method includes securing the semiconductor substrate by a wafer electrostatic-clamp. The method also includes patterning the photoresist layer by emitting radiation from a radiation source via the reticle.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Lun Chang, Chueh-Chi Kuo, Tsung-Yen Lee, Tzung-Chi Fu, Li-Jui Chen, Po-Chung Cheng, Che-Chang Hsu
  • Patent number: 11985906
    Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
  • Patent number: 11983475
    Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
  • Patent number: 11983046
    Abstract: A portable information handling system pivots a hinge rotational axis as the hinge rotates housing portions between open and closed positions to manage a gap between the housing portions. For example, the hinge couples a base at a perimeter of one housing portion, the base having a many body that slides on sliding members of the base and that supports a bracket extending inward to couple to another housing portion. A bracket gear engages with a pinion gear included in the main body to translate bracket rotation through the pinion gear to a rack integrated in the base, thereby sliding the main body relative to the base as the housing portions rotate so that the distance between the housing portions adjusts with rotational orientation.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 14, 2024
    Assignee: Dell Products L.P.
    Inventors: Anthony J. Sanchez, Michael J. Pescetto, Boris Draca, Hsin-Chung Chang, Jui-Hung Chang
  • Patent number: 11981468
    Abstract: A plastic thread bonding method and structure for folding edge of a FIBC includes setting the folding edge of the FIBC flatly on a metal solid surface; using a cooling device to maintain a condensation temperature of the solid surface; performing a needle insertion action of the folding edge by a plastic injection needle, and condensing and crystallizing at the eyelet to form a base point; performing a needle withdrawal action by the plastic injection needle to fill up a melted plastic into the eyelet, applying a pressurized cold air to condense the melted plastic to from a thread post; performing a horizontal translation action of the plastic injection needle or the folding edge, and applying the pressurized cold air to condense the melted plastic to form a thread bridge; and repeating the aforementioned procedure to form a next base point, a next thread post and a thread bridge.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 14, 2024
    Assignee: HON BOUW CO., LTD.
    Inventor: Pao-Chung Chang
  • Patent number: 11982798
    Abstract: A projection lens includes a first lens group, a second lens group and an aperture stop. The first lens group is disposed between a reduced side and a magnified side. The second lens is disposed between the first lens group and the magnified side. The second lens group has a light incident surface, a reflective surface and a light emitting surface, the light incident surface faces the first lens group, the light emitting surface faces a projection surface, the light incident surface, the light emitting surface and the first lens group are disposed at a single side of the reflective surface, and at least one of the light incident surface, the reflective surface and the light emitting surface is a freeform surface. The aperture stop is disposed between the first lens group and the second lens group. Moreover, a projection apparatus including the projection lens is also provided.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: May 14, 2024
    Assignee: Coretronic Corporation
    Inventors: Hsin-Hsiang Lo, Wei-Ting Wu, Fu-Ming Chuang, Chuan-Chung Chang, Ching-Chuan Wei
  • Publication number: 20240154021
    Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 9, 2024
    Inventors: TING-CHANG CHANG, Wei-Chen Huang, Shih-Kai Lin, Yong-Ci Zhang, Sheng-Yao Chou, Chung-Wei Wu, Po-Hsun Chen
  • Publication number: 20240148280
    Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Chien-Chung Chen
  • Patent number: 11974842
    Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 7, 2024
    Assignee: Bionime Corporation
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Chien-Chung Chen
  • Patent number: 11979971
    Abstract: An extreme ultra violet (EUV) radiation source apparatus includes a collector mirror, a target droplet generator for generating a tin (Sn) droplet, a rotatable debris collection device, one or more coils for generating an inductively coupled plasma (ICP), a gas inlet for providing a source gas for the ICP, and a chamber enclosing at least the collector mirror and the rotatable debris collection device. The gas inlet and the one or more coils are configured such that the ICP is spaced apart from the collector mirror.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Shuo Su, Chun-Lin Chang, Han-Lung Chang, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 11978802
    Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wei Hsu, Chih-Hao Wang, Huan-Chieh Su, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu
  • Publication number: 20240139142
    Abstract: Provided is a method for preventing or treating a liver disease, including administering a therapeutically effective amount of pharmaceutical composition to a subject in need, and the pharmaceutical composition includes the isothiocyanate structural modified compound and a pharmaceutically acceptable carrier thereof.
    Type: Application
    Filed: September 14, 2023
    Publication date: May 2, 2024
    Applicants: TAIPEI VETERANS GENERAL HOSPITAL, NATIONAL YANG MING CHIAO TUNG UNIVERSITY, PHARMAESSENTIA CORPORATION
    Inventors: Jaw-Ching WU, Yung-Sheng CHANG, Kuo-Hsi KAO, Chan-Kou HWANG, Ko-Chung LIN
  • Publication number: 20240145554
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Patent number: 11973260
    Abstract: A light-transmitting antenna includes a substrate, a first and a second conductive pattern. The first and the second conductive pattern is disposed on a first and a second surface of the substrate respectively. The first conductive pattern includes a first feeder unit, a first and a second radiation unit, a first and a second coupling unit and a first parasitic unit. The first feeder unit is connected to the second radiation unit. The first and the second radiation unit are located between the first and the second coupling unit. One side and the other side of the first parasitic unit is connected to the second coupling unit and adjacent to the first coupling unit respectively. The second conductive pattern includes a second feeder unit, a third coupling unit, a second parasitic unit, and a fourth coupling unit.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 30, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Ruo-Lan Chang, Mei-Ju Lee, Cheng-Hua Tsai, Meng-Hsuan Chen, Wei-Chung Chen
  • Publication number: 20240131538
    Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
  • Patent number: 11966628
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20240128122
    Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chung Chang, Ming-Che Ho, Hung-Jui Kuo