Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: The present invention relates to an optical system for triglyceride inspection partially integrated into a toilet seat and comprising a plurality of optical sensor modules and a controlling and processing module, wherein each said optical sensor module comprises a first light source, a second light source and an optical sensor. The optical sensor receives light signals generated by the first and second light sources respectively on the skin of the person (especially the skin of the thighs) to be tested and thereby generates a sensing signal of an adaptive calibration function. The sensing signal is then converted by the controlling and processing module into an inspection value of triglyceride, which is transmitted to a display unit. With the above optical system for triglyceride inspection, triglycerides can be inspected automatically without invasive blood sampling, making the system a convenient home health monitoring device.

Abstract: Cement bonding evaluation and logging in a wellbore environment are described. The cement bonding evaluation is performed using data associated with and processed from the measurement of sonic waves directed to and dissipated by the casing present in the wellbore.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: Disclosed herein is a method for eccentricity correction. This method may dispose a downhole tool into a borehole. The downhole tool may comprise a measuring assembly that has at least one transducer, determining a beam pattern from the at least one transducer, determining a center of the measurement assembly in the borehole with the beam pattern, calculating a beam pattern factor with at least the beam pattern, calculating an angle factor with at least the beam pattern, calculating an eccentricity factor with at least the beam pattern factor and the angle factor, and creating an eccentricity corrected image with at least the eccentricity factor.

Abstract: A non-metal spring includes two non-metal elastic units connected to each other and formed between two non-metal terminal rings. Each of the non-metal elastic units includes two intermediate rings intersecting each other, thereby providing two cross portions. The cross portions of each of the non-metal elastic units divide each of the intermediate rings into a first portion and a second portion. The first portions of the intermediate rings of one of the non-metal elastic units are connected to one of the terminal rings. The second portions of the intermediate rings of another one of the non-metal elastic units are connected to a remaining one of the terminal rings. The first portions of the intermediate rings of each of the non-metal elastic units are connected to the second portions of the intermediate rings of an adjacent one of the non-metal elastic units.

Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate. The protective layer and the photoresist layer are selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer. The protective layer includes a polymer without a nitrogen-containing moiety, and a basic quencher, an organic acid, a photoacid generator, or a thermal acid generator.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: The present disclosure relates to a pad surface cleaning system to be used with a conditioning module to condition a polishing surface of a polishing pad. The pad surface cleaning system may be used to spray the polishing surface with a high-pressure fluid spray to loosen debris from the polishing surface. The pad surface cleaning system may also be used to remove the loosened debris. Further, the pad surface cleaning system may isolate a conditioning disk from a polishing fluid to protect the conditioning disk from reacting with the polishing fluid.

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value

Abstract: An integrated circuit includes a first power rail and a second power rail extending in a first direction, and a first power grid stub connected to the first power rail through a first via-connector. The integrated circuit also includes a first vertical conducting line extending in a second direction in a circuit cell between a first vertical cell boundary and a second vertical cell boundary. The first vertical conducting line and the first power grid stub are in a same metal layer and aligned with each other along the second direction.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: A training device and a training method for reducing hypertonic are disclosed. The training device includes a base, a driving circuit, two pedals, a control circuit, and a switch circuit. The driving circuit is fixed on the base. Each of the two pedals is coupled to the base. The driving circuit drives each of the two pedals to swing repeatedly between a first position and a second position relative to the base. When the control circuit executes a training program, the control circuit actuates the driving circuit.

Abstract: A power supply with a separable communication module includes a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module includes a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface, and a second state of detaching from the first interface.

Abstract: A signal enhancement structure configured to enhance a signal of a specimen is provided. The signal enhancement structure includes a plurality of nanowires stacked in a first direction, a second direction, and a third direction. The nanowires are extended along at least two directions. A particle of the specimen is on the nanowires or in a gap among the nanowires. A manufacturing method of a signal enhancement structure and a measuring method with signal enhancement are also provided.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: An optical module is provided, including a movable portion, a fixed portion, and a circuit assembly. The movable portion is configured to connect an optical member, and is movable relative to the fixed portion. Moreover, the movable portion is movably connected to the fixed portion via the circuit assembly.

Abstract: An in-cell optical sensing display panel includes a pixel array, a plurality of first optical sensors and a plurality of second optical sensors. The pixel array is disposed in an active area of the in-cell optical sensing display panel, and the active area includes a first region and a second region which surrounds the first region. The sensor array is disposed in the first region of the active area and is configured to sense a fingerprint of a finger touching a surface of the in-cell optical sensing display panel. The second optical sensors are disposed in the second region of the active area and are configured to sense ambient light, and the second optical sensors are not to be used for fingerprint sensing.