Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: A device is provided, which includes a wiring structure including a first surface and a second surface opposite the first surface. The device also includes a first semiconductor die on the first surface of the wiring structure where the first semiconductor die includes first power amplifier unit. The device further includes a second semiconductor die on the first surface of the wiring structure where the second semiconductor has a second power amplifier unit and is spaced apart from the first semiconductor die. In addition, the device includes a first input port at the second surface of the wiring structure, and a first conductor in the wiring structure to electrically connect the first input port to the first semiconductor die and the second semiconductor die.

Abstract: Among other things, one or more techniques and systems for selectively filtering RF signals within one or more RF frequency band are provided. In particular, an RF choke, such as a 3D RF choke or a semi-lumped RF choke, configured to selectively filter such RF signals is provided. The RF choke comprises a metal connection line configured as an inductive element for the RF choke. In an example, one or more metal lines, such as a metal open stub, are formed as capacitive elements for the RF choke. In another example, one or more through vias are formed as capacitive elements for the RF choke. In this way, the RF choke allows DC power signals to pass through the metal connection line, while impeding RF signals within the one or more RF frequency bands from passing through the metal connection line.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.

Abstract: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: The present invention provides a device for suppressing common-mode radiation comprising: at least one resonator embedded into a plate, wherein the at least one resonator defines a plane having a normal direction parallel and perpendicular, respectively, to a longitudinal direction and a thickness direction of the plate. The embedment of the resonator into the plate enables a magnetic field, which is generated by a cable conductor when the device for suppressing common-mode radiation wraps the cable conductor therein, to perpendicularly pass through the plane so that the magnetic field and the resonator resonate together to generate a strong diamagnetism and thereby to suppress the common-mode radiation.

Abstract: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.

Abstract: An integrated fan out (InFO) antenna includes a reflector on a surface of a substrate; and a package. The package includes a redistribution layer (RDL) arranged to form an antenna ground, and a patch antenna over the RDL, wherein the RDL is between the patch antenna and the reflector. The InFO antenna further includes a plurality of connecting elements bonding the package to the reflector. Each connecting element of the plurality of connecting elements is located inside an outer perimeter of the reflector. The InFO antenna is configured to output a signal having a wavelength.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.

Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: Embodiments of mechanisms for forming a semiconductor die are provided. The semiconductor die includes a semiconductor substrate and a protection layer formed over the semiconductor substrate. The semiconductor die also includes a conductive layer conformally formed over the protection layer, and a recess is formed in the conductive layer. The recess surrounds a region of the conductive layer. The semiconductor die further includes a solder bump formed over the region of the conductive layer surrounded by the recess.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.

Abstract: A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.

Abstract: Embodiments of mechanisms for forming a semiconductor die are provided. The semiconductor die includes a semiconductor substrate and a protection layer formed over the semiconductor substrate. The semiconductor die also includes a conductive layer conformally formed over the protection layer, and a recess is formed in the conductive layer. The recess surrounds a region of the conductive layer. The semiconductor die further includes a solder bump formed over the region of the conductive layer surrounded by the recess.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: This invention provides a digital electronic device comprising: a grounded metal portion comprising a first metal plate electrically connected to ground and a first substrate disposed on the first metal plate; at least one layer of differential-mode reference metal portion comprising a second substrate and a second metal plate electrically connected to the first metal plate by at least one conductive structure; a pair of differential signal lines at least partially disposed on the second substrate of the at least one layer of differential-mode reference metal portion and electromagnetically coupled to the second metal plate of the at least one layer of differential-mode reference metal portion; and an equalizer electrically connected to the pair of differential signal lines.