Patents by Inventor Chung-Hao Tsai
Chung-Hao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180366344Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.Type: ApplicationFiled: June 18, 2017Publication date: December 20, 2018Applicant: Powertech Technology Inc.Inventors: Kun-Yung Huang, Chih-Fu Lung, Shih-Chi Li, Mei-Chen Lee, Chung-Hao Tsai, Chi-Liang Wang
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Patent number: 10157791Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.Type: GrantFiled: September 19, 2014Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
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Patent number: 10157834Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.Type: GrantFiled: September 18, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chun Tang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
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Patent number: 10153239Abstract: A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with the metal ring, encapsulating the device die and the metal ring in an encapsulating material. The method further includes filling a dielectric material into a space encircled by the metal ring, and forming a second metal plate covering the dielectric material and the metal ring, with an opening formed in the second metal plate. A plurality of redistribution lines is formed, with one of the redistribution lines overlapping a portion of the opening. The first metal plate, the metal ring, the second metal plate, and the dielectric material in combination form an antenna or a waveguide. The redistribution line forms a signal-coupling line of the passive device.Type: GrantFiled: August 4, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Jeng-Shien Hsieh, Wei-Heng Lin
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Publication number: 20180337159Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
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Patent number: 10134708Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.Type: GrantFiled: August 5, 2016Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
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Publication number: 20180158787Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor.Type: ApplicationFiled: December 2, 2016Publication date: June 7, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shou-Zen Chang, Chung-Hao Tsai, Chuei-Tang Wang, Kai-Chiang Wu, Ming-Kai Liu
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Publication number: 20180138126Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.Type: ApplicationFiled: November 17, 2016Publication date: May 17, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin CHEN, Chung-Hao TSAI, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU, Chih-Yuan CHANG
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Publication number: 20180108477Abstract: A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.Type: ApplicationFiled: September 18, 2017Publication date: April 19, 2018Inventors: Monsen LIU, Chung-Hao TSAI, En-Hsiang YEH, Chuei-Tang WANG, Chen-Hua YU
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Publication number: 20180102595Abstract: A semiconductor device includes an active device. The semiconductor device further includes a plurality of antenna grounds electrically connected to the active device. The semiconductor device further includes a plurality of patch antennas, wherein each patch antenna of the plurality of patch antennas is over a corresponding antenna ground of the plurality of antenna grounds. The semiconductor device further includes a plurality of reflectors, wherein each antenna ground of the plurality of antenna ground is between a corresponding patch antenna of the plurality of patch antennas and a corresponding reflector of the plurality of reflectors. An area of each antenna ground of the plurality of antenna grounds is greater than an area of each reflector of the plurality of reflectors.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Inventors: Chuei-Tang WANG, Jeng-Shieh HSIEH, Chung-Hao TSAI, Monsen LIU, Chen-Hua YU
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Publication number: 20180040585Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.Type: ApplicationFiled: August 5, 2016Publication date: February 8, 2018Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
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Patent number: 9843106Abstract: An integrated fan out (InFO) antenna includes a reflector on a surface of a substrate; and a package. The package includes a redistribution layer (RDL) arranged to form an antenna ground, and a patch antenna over the RDL, wherein the RDL is between the patch antenna and the reflector. The InFO antenna further includes a plurality of connecting elements bonding the package to the reflector. Each connecting element of the plurality of connecting elements is located inside an outer perimeter of the reflector. The InFO antenna is configured to output a signal having a wavelength.Type: GrantFiled: October 9, 2014Date of Patent: December 12, 2017Assignee: TAIWAN SEMICONDCUTOR MANUFACTURING COMPANY, LTD.Inventors: Chuei-Tang Wang, Jeng-Shieh Hsieh, Chung-Hao Tsai, Monsen Liu, Chen-Hua Yu
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Publication number: 20170346185Abstract: An antenna device includes a package and at least one antenna. The package includes at least one radio frequency (RF) die and a molding compound in contact with at least one sidewall of the RF die. The antenna has at least one conductor at least partially in the molding compound and operatively connected to the RF die.Type: ApplicationFiled: August 23, 2016Publication date: November 30, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chuei-Tang WANG, Chung-Hao TSAI, Jeng-Shien HSIEH, Wei-Heng LIN, Kuo-Chung YEE, Chen-Hua YU
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Publication number: 20170338195Abstract: A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with the metal ring, encapsulating the device die and the metal ring in an encapsulating material. The method further includes filling a dielectric material into a space encircled by the metal ring, and forming a second metal plate covering the dielectric material and the metal ring, with an opening formed in the second metal plate. A plurality of redistribution lines is formed, with one of the redistribution lines overlapping a portion of the opening. The first metal plate, the metal ring, the second metal plate, and the dielectric material in combination form an antenna or a waveguide. The redistribution line forms a signal-coupling line of the passive device.Type: ApplicationFiled: August 4, 2017Publication date: November 23, 2017Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Jeng-Shien Hsieh, Wei-Heng Lin
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Patent number: 9773730Abstract: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.Type: GrantFiled: January 8, 2016Date of Patent: September 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
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Patent number: 9767957Abstract: A method making a three-dimensional inductor, the method including: forming a plurality of vias in a substrate or a molding compound, wherein the vias are arranged with spacings among them; forming a metal layer having interconnects, wherein the interconnects of the metal layer connect the plurality of vias on one end of the vias; forming a plurality of wires to connect the plurality of vias on the other end of the vias to form the 3D inductor; and tuning one or more of the plurality of wires to adjust a physical configuration and inductance value of the 3D inductor.Type: GrantFiled: August 12, 2013Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Monsen Liu, Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
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Patent number: 9735118Abstract: A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with the metal ring, encapsulating the device die and the metal ring in an encapsulating material. The method further includes filling a dielectric material into a space encircled by the metal ring, and forming a second metal plate covering the dielectric material and the metal ring, with an opening formed in the second metal plate. A plurality of redistribution lines is formed, with one of the redistribution lines overlapping a portion of the opening. The first metal plate, the metal ring, the second metal plate, and the dielectric material in combination form an antenna or a waveguide. The redistribution line forms a signal-coupling line of the passive device.Type: GrantFiled: December 4, 2015Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Jeng-Shien Hsieh, Wei-Heng Lin
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Publication number: 20170162524Abstract: A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with the metal ring, encapsulating the device die and the metal ring in an encapsulating material. The method further includes filling a dielectric material into a space encircled by the metal ring, and forming a second metal plate covering the dielectric material and the metal ring, with an opening formed in the second metal plate. A plurality of redistribution lines is formed, with one of the redistribution lines overlapping a portion of the opening. The first metal plate, the metal ring, the second metal plate, and the dielectric material in combination form an antenna or a waveguide. The redistribution line forms a signal-coupling line of the passive device.Type: ApplicationFiled: December 4, 2015Publication date: June 8, 2017Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Jeng-Shien Hsieh, Wei-Heng Lin
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Patent number: 9640457Abstract: A device is provided, which includes a wiring structure including a first surface and a second surface opposite the first surface. The device also includes a first semiconductor die on the first surface of the wiring structure where the first semiconductor die includes first power amplifier unit. The device further includes a second semiconductor die on the first surface of the wiring structure where the second semiconductor has a second power amplifier unit and is spaced apart from the first semiconductor die. In addition, the device includes a first input port at the second surface of the wiring structure, and a first conductor in the wiring structure to electrically connect the first input port to the first semiconductor die and the second semiconductor die.Type: GrantFiled: January 20, 2015Date of Patent: May 2, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang
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Publication number: 20170098883Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: Jeng-Shien Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu