Abstract: A data processing apparatus of a basic input/output system (BIOS) is provided. The data processing apparatus includes a BIOS unit, a share memory and a control unit. The BIOS unit writes command data into the share memory, wherein the command data includes identification data stored in an identification field. The control unit reads and performs the command data according to the identification data in the identification field. After the command data is performed, the control unit writes returned data into the share memory for the BIOS unit to read the returned data, wherein the returned data includes the execution result of the command data performed by the control unit and also includes the identification data.

Abstract: An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.

Abstract: An integrated circuit includes a first pass gate and a first receiver electrically coupled with the first pass gate. The first receiver includes a first N-type transistor. A first gate of the first N-type transistor is electrically coupled with the first pass gate. A first P-type bulk of the first N-type transistor is surrounded by a first N-type doped region. The first N-type doped region is surrounded by a first N-type well. The first N-type doped region has a dopant concentration higher than that of the first N-type well.

Abstract: An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor.

Abstract: A data processing apparatus of a basic input/output system (BIOS) is provided. The data processing apparatus includes a BIOS unit, a share memory and a control unit. The BIOS unit writes command data into the share memory, wherein the command data includes identification data stored in an identification field. The control unit reads and performs the command data according to the identification data in the identification field. After the command data is performed, the control unit writes returned data into the share memory for the BIOS unit to read the returned data, wherein the returned data includes the execution result of the command data performed by the control unit and also includes the identification data.

Abstract: A high-speed digital level shifter is described. The preferred embodiment shifts an input signal with a lower amplitude to a signal with a higher amplitude. The level shifter includes a signal driver circuit to drive up the input signal to a driver signal having higher voltages. The driver signal is used to drive an output circuit that generates an output signal having amplitude of a high voltage power source. The output circuit has improved performance being driven by the driver input signal. A signal stepper is added to further improve the performance by pulling up the output voltage in two stages.

Abstract: The present invention discloses an apparatus for detecting a current flowing from a first node to a second node. One or more MOS devices are serially coupled between the first and second nodes. Each of the MOS devices has its body connected to its source and its gate connected to its drain for providing each MOS device with a voltage difference between its gate and its source that is lower than a threshold voltage of the same, such that a voltage difference measured between the first and second nodes responds to a change of the current exponentially.

Abstract: An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor.

Abstract: A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the second data read from the memory apparatus, the process issues the read second data request first, followed by the write-back first data request. The detector provides a detecting signal when the processor issues the read second data request and cancels the provided detecting signal when the processor issues the write-back first data request. Each pass-gate decides whether to pass the third access request outputting from each corresponding access-consumer and transmit it to the memory apparatus according to the detecting signal respectively.

Abstract: Disclosed herein are a capacitive circuit for use on a semiconductor substrate, and related method of manufacturing the same. In one aspect, the capacitive circuit includes a plurality of MOSFETs each having their respective source and drain electrically coupled together, where the plurality of MOSFETs are series-coupled to each other by electrically coupling a gate of one of the plurality to the coupled source/drain of another of the plurality. In this embodiment, the circuit also includes a power supply electrically coupled to the plurality of MOSFETs, where a coupled source/drain of one of the plurality of MOSFETs at a first end of the series is electrically coupled to a first terminal of the power supply, and a gate of another of the plurality of MOSFETs at a second end of the series is electrically coupled to a second terminal of the power supply. The circuit also includes a plurality of resistive elements each electrically parallel-coupled across corresponding ones of the plurality of MOSFETs.

Abstract: This invention discloses a method of controlling the multimedia audio and video playback by installing an audio/video playback program, a playback control program, and a data storage medium in a computer device, wherein the audio/video playback program adjusts a setup value for each of the playback setup options and saves the adjusted setup value into the data storage medium, such that after the computer device is booted every time, the playback control program detects the execution of the audio/video playback program and determines whether or not a multimedia file is waiting to be executed; if yes, it loads the setup value of the playback setup option from the data storage medium, so that the audio/video playback program can play the multimedia file according to the content of the setup value.

Abstract: A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher.

Abstract: A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a circuit-under-test in the system. The system further includes a unit circuit having a plurality of input terminal couple to a plurality of signal path respectively, and an output terminal couple to the circuit-under-test. A selection and activation circuit of the BIST circuit having an output terminal couple to one of input terminals of the unit circuit, one input terminal couple to a non-timing-critical path of the signal paths, and the other input terminal receives a test signal. When the system operates in a test mode, the BIST controller provides the test signal through the selection and activation circuit and the unit circuit to test the circuit-under-test.

Abstract: The present invention discloses an apparatus for detecting a current flowing from a first node to a second node. One or more MOS devices are serially coupled between the first and second nodes. Each of the MOS devices has its body connected to its source and its gate connected to its drain for providing each MOS device with a voltage difference between its gate and its source that is lower than a threshold voltage of the same, such that a voltage difference measured between the first and second nodes responds to a change of the current exponentially.

Abstract: An electrostatic discharge protection (ESD) circuit is disclosed for protecting a pad of an integrated circuit from ESD events. The ESD circuit has an ESD trigger module having a first and second transistors connected in series, between the pad and a first common node, at least one ESD protection module having a third and fourth transistors connected in series between the pad and a second common node, and a current limiting resistor in the ESD trigger module connected between the first and second common nodes, wherein the first and second transistors have a shorter channel length than that of the third and fourth transistors so that the ESD trigger module is turned on before the ESD protection module when an ESD event happens on the pad.

Abstract: An improved clock lock detection circuit is disclosed. The circuit has a first input indicating an edge of a first clock and a second input indicating a corresponding edge of a second clock wherein the second clock is expected to be synchronized with the first clock with an allowable time difference. Further, it has a difference generation module for generating a difference signal based on the time difference between the first and second inputs, and a voltage divider module for receiving the difference signal and generating an indication voltage which varies based on a change of the time difference between the first and second inputs.

Abstract: A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the second data read from the memory apparatus, the process issues the read second data request first, followed by the write-back first data request. The detector provides a detecting signal when the processor issues the read second data request and cancels the provided detecting signal when the processor issues the write-back first data request. Each pass-gate decides whether to pass the third access request outputting from each corresponding access-consumer and transmit it to the memory apparatus according to the detecting signal respectively.

Abstract: A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a circuit-under-test in the system. The system further includes a unit circuit having a plurality of input terminal couple to a plurality of signal path respectively, and an output terminal couple to the circuit-under-test. A selection and activation circuit of the BIST circuit having an output terminal couple to one of input terminals of the unit circuit, one input terminal couple to a non-timing-critical path of the signal paths, and the other input terminal receives a test signal. When the system operates in a test mode, the BIST controller provides the test signal through the selection and activation circuit and the unit circuit to test the circuit-under-test.

Abstract: A system and method is disclosed for providing a bandgap reference voltage generator that can successfully operate with a low operating voltage. Three current sources are controlled to provide same amount of current through three paths. The first current source is used to enable a first negative temperature coefficient module, while the second and third current sources are used to enable a first positive temperature coefficient module. The three current sources together are used to enable a reference voltage output module, which is connected to a current summing module for producing a bandgap reference voltage independent of temperature variations.