Abstract: A system and method is disclosed for providing a bandgap reference voltage generator that can successfully operate with a low operating voltage. Three current sources are controlled to provide same amount of current through three paths. The first current source is used to enable a first negative temperature coefficient module, while the second and third current sources are used to enable a first positive temperature coefficient module. The three current sources together are used to enable a reference voltage output module, which is connected to a current summing module for producing a bandgap reference voltage independent of temperature variations.

Abstract: A high speed receiver circuit is disclosed with a high supply voltage and operable with other circuits operating at a low supply voltage. The receiver circuit comprises first and second differential input signals controlling first and second current switches. It also includes a top current supply connected to the high supply voltage for providing a current to be passed either through the first current switch and a first bottom current supply or the second current switch and a second bottom current supply. Further included are first and second resistors connected to the low supply voltage and in a series with the first or second bottom current supplies respectively. First and second differential output signals are produced at a point between each pair of the resistors and the bottom current supply. A common mode voltage of the first and second differential output signals is lower than the low supply voltage.

Abstract: A programmable memory circuit and a method for programming the same are disclosed. A polycrystalline silicon resistor pair are used in a programmable memory cell. The pair includes a first polycrystalline silicon resistor stressable by a predetermined current thereacross, and a second polycrystalline silicon resistor similarly structured as the first polycrystalline silicon resistor stressable by the predetermined current, wherein when only the first resistor is stressed by the predetermined current, a resistance of the first resistor is lowered as compared to the unstressed second resistor, thereby programming the memory cell.

Abstract: An eletrostatic discharge (ESD) protection circuit and method for operating same are disclosed. The protection circuit for each pad of integrated circuits include a diode string connected to a first pad at its anode end having a total forward voltage drop more than, or equal to, a first supply voltage and with its cathode end passing the ESD charge, a current dissipation module with at least one N-type MOSFET for passing the ESD charge from diode string to a first common node connectable to a second supply voltage, a first diode with its anode end connected to first common node and its cathode node connected to the first pad, and a control module for controlling the current dissipation module for dissipating the ESD charge through the first common node when it causes a voltage on the first pad to surpass the total forward voltage drop of the diode string.

Abstract: A programmable metal-oxide-semiconductor (MOS) memory circuit and the method for programming same and disclosed. The circuit comprises a first N-type transistor having a gate region tied with a drain region and connectable to a first control voltage level, and a source region connected to a second voltage level; and a second N-type transistor having a gate region tied with a drain region and connectable to the first control voltage level, and a source region connected to the second voltage level, wherein the first and second control voltage levels are imposed to program either the first or second N-type transistor by causing a voltage difference between the drain region and the source region (Vds) and voltage difference between the gate region and the source region (Vgs) to be bigger than a predetermined threshold voltage to induce a hot carrier effect.

Abstract: The present invention comprises an ESD clamp circuit used in an integrated circuit with plural power supply. The ESD clamp circuit, connected between core voltage source and low voltage source, is fabricated by a process which fabricates core circuit. The ESD clamp circuit has a low trigger voltage, so it can conduct large current to protect the core circuit before the core circuit is damaged.

Abstract: The invention describes structures and a process for providing ESD semiconductor protection with reduced input capacitance that has special advantages for high frequency analog pin I/O applications. The structures consist of a first and second NMOS serial pair whose capacitance is shielded from the I/O pins by a serial diode. The first serial pair provides an ESD voltage clamp between the I/O pin and the Vcc voltage source. The second pair provides an ESD voltage clamp between the I/O pin and Vss, or ground voltage source. A NMOS device whose gate is dynamically coupled to the ESD energy through capacitance and a RC network enhances the triggering of both pairs. The serial pairs can be used separately to match specific application requirements or used together.

Abstract: An ESD protection circuit includes a stacked NMOS transistor pair coupled between a pad and a negative voltage supply, with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply. A first voltage divider provides reduced voltage from a high voltage positive power supply to a gate of the first transistor, a first diode string coupled between the gates of the first and second transistors, a second diode string with its anode coupled to the pad, an inverter with a source of its PMOS transistor coupled to a cathode of the second diode string and with its NMOS transistor coupled to the negative power supply, an output node of the inverter coupled to a gate of the second transistor, and a RC circuit coupled to an input node of the inverter, for dissipation of ESD current.

Abstract: A high-speed digital level shifter is described. The preferred embodiment shifts an input signal with a lower amplitude to a signal with a higher amplitude. The level shifter includes a signal driver circuit to drive up the input signal to a driver signal having higher voltages. The driver signal is used to drive an output circuit that generates an output signal having amplitude of a high voltage power source. The output circuit has improved performance being driven by the driver input signal. A signal stepper is added to further improve the performance by pulling up the output voltage in two stages.

Abstract: Disclosed herein are a capacitive circuit for use on a semiconductor substrate, and related method of manufacturing the same. In one aspect, the capacitive circuit includes a plurality of MOSFETs each having their respective source and drain electrically coupled together, where the plurality of MOSFETs are series-coupled to each other by electrically coupling a gate of one of the plurality to the coupled source/drain of another of the plurality. In this embodiment, the circuit also includes a power supply electrically coupled to the plurality of MOSFETs, where a coupled source/drain of one of the plurality of MOSFETs at a first end of the series is electrically coupled to a first terminal of the power supply, and a gate of another of the plurality of MOSFETs at a second end of the series is electrically coupled to a second terminal of the power supply. The circuit also includes a plurality of resistive elements each electrically parallel-coupled across corresponding ones of the plurality of MOSFETs.

Abstract: An electrostatic discharge protection (ESD) circuit is disclosed for protecting a pad of an integrated circuit from ESD events. The ESD circuit has an ESD trigger module having a first and second transistors connected in series, between the pad and a first common node, at least one ESD protection module having a third and fourth transistors connected in series between the pad and a second common node, and a current limiting resistor in the ESD trigger module connected between the first and second common nodes, wherein the first and second transistors have a shorter channel length than that of the third and fourth transistors so that the ESD trigger module is turned on before the ESD protection module when an ESD event happens on the pad.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed for preventing a pad-to-pad ESD charge. The protection circuit for each pad of an integrated circuit comprises a current dissipation module with an N-type MOSFET connected in parallel with a bipolar junction transistor (BJT) wherein the drain of the MOSFET and the collector of the BJT are connected to a first common node and the source of the MOSFET and the emitter of the BJT are connected to a second common node connectable to a second operating voltage. A diode string is connected to a first pad at its anode end having a total forward voltage drop more than a first operating voltage and with its cathode end connected to the body of the MOSFET, the base of the BJT, and to the second common node through a resistor.

Abstract: An ESD protection circuit includes a stacked NMOS transistor pair coupled between a pad and a negative voltage supply, with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply. A first voltage divider provides reduced voltage from a high voltage positive power supply to a gate of the first transistor, a first diode string coupled between the gates of the first and second transistors, a second diode string with its anode coupled to the pad, an inverter with a source of its PMOS transistor coupled to a cathode of the second diode string and with its NMOS transistor coupled to the negative power supply, an output node of the inverter coupled to a gate of the second transistor, and a RC circuit coupled to an input node of the inverter, for dissipation of ESD current.

Abstract: A high speed receiver circuit is disclosed with a high supply voltage and operable with other circuits operating at a low supply voltage. The receiver circuit comprises first and second differential input signals controlling first and second current switches. It also includes a top current supply connected to the high supply voltage for providing a current to be passed either through the first current switch and a first bottom current supply or the second current switch and a second bottom current supply. Further included are first and second resistors connected to the low supply voltage and in a series with the first or second bottom current supplies respectively. First and second differential output signals are produced at a point between each pair of the resistors and the bottom current supply. A common mode voltage of the first and second differential output signals is lower than the low supply voltage.

Abstract: A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher.

Abstract: An eletrostatic discharge (ESD) protection circuit and method for operating same are disclosed. The protection circuit for each pad of integrated circuits include a diode string connected to a first pad at its anode end having a total forward voltage drop more than, or equal to, a first supply voltage and with its cathode end passing the ESD charge, a current dissipation module with at least one N-type MOSFET for passing the ESD charge from diode string to a first common node connectable to a second supply voltage, a first diode with its anode end connected to first common node and its cathode node connected to the first pad, and a control module for controlling the current dissipation module for dissipating the ESD charge through the first common node when it causes a voltage on the first pad to surpass the total forward voltage drop of the diode string.

Abstract: A system and method is disclosed for providing a bandgap reference voltage generator that can successfully operate with a low operating voltage. Three current sources are controlled to provide same amount of current through three paths. The first current source is used to enable a first negative temperature coefficient module, while the second and third current sources are used to enable a first positive temperature coefficient module. The three current sources together are used to enable a reference voltage output module, which is connected to a current summing module for producing a bandgap reference voltage independent of temperature variations.

Abstract: A programmable metal-oxide-semiconductor (MOS) memory circuit and the method for programming same and disclosed. The circuit comprises a first N-type transistor having a gate region tied with a drain region and connectable to a first control voltage level, and a source region connected to a second voltage level; and a second N-type transistor having a gate region tied with a drain region and connectable to the first control voltage level, and a source region connected to the second voltage level, wherein the first and second control voltage levels are imposed to program either the first or second N-type transistor by causing a voltage difference between the drain region and the source region (Vds) and voltage difference between the gate region and the source region (Vgs) to be bigger than a predetermined threshold voltage to induce a hot carrier effect.

Abstract: An improved clock lock detection circuit is disclosed. The circuit has a first input indicating an edge of a first clock and a second input indicating a corresponding edge of a second clock wherein the second clock is expected to be synchronized with the first clock with an allowable time difference. Further, it has a difference generation module for generating a difference signal based on the time difference between the first and second inputs, and a voltage divider module for receiving the difference signal and generating an indication voltage which varies based on a change of the time difference between the first and second inputs.

Abstract: A double-edge-trigger flip-flop comprising a first pass gate controlled by a clock signal and an inverted signal of the clock for passing an input; a second pass gate controlled by the clock signal and the inverted signal of the clock for passing the input in a complementary manner with regard to the first pass gate; a first signal passing module for further passing the input passed by the first pass gate into a third pass gate controlled by the clock signal and the inverted signal of the clock for generating a first part of an output of the flip-flop, wherein the third pass gate passes the input in a complementary manner with regard to the first pass gate; and a second signal passing module for further passing the input passed by the second pass gate into a fourth pass gate controlled by the clock signal and the inverted signal of the clock for generating a second part of the output, wherein the fourth pass gate passes the input in a complementary manner with regard to the second pass gate.