Patents by Inventor Chung-Hui Chen

Chung-Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MOS-BASED VOLTAGE REFERENCE CIRCUIT
    Publication number: 20150115717
    Abstract: A voltage reference circuit is provided that includes a first circuit, a second circuit and a third circuit. The first circuit has a first MOS transistor pair and the second circuit has a second MOS transistor pair. The first circuit is configured to provide a first voltage component that changes at a first rate having a first slope as a temperature to which the voltage reference circuit is subjected changes. The second circuit is configured to provide a second voltage component that changes at a second rate having a second slope as the temperature changes. The third circuit is configured to use the first voltage component and the second voltage component to generate the reference voltage component that changes at a fifth rate having a fifth slope as the temperature changes. The fifth slope is substantially equal to zero to promote insensitivity of the reference voltage component to temperature changes.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaw-Juinn Horng, Amit Kundu, Chung-Hui Chen, Yung-Chow Peng
  • Diode structures using fin field effect transistor processing and method of forming the same
    Patent number: 8946038
    Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Sun-Jay Chang, Jaw-Juinn Horng, Chung-Hui Chen
  • GENERATING A SEMICONDUCTOR COMPONENT LAYOUT
    Publication number: 20150007122
    Abstract: A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 1, 2015
    Inventors: Chien-Hung CHEN, Yung-Chow PENG, Chung-Hui CHEN, Chih-Ming YANG
  • THERMAL SENSOR
    Publication number: 20140369381
    Abstract: A circuit includes a comparator unit and a switching network. The comparator unit is configured to receive a first voltage value, a second voltage value and a third voltage value of a voltage node, and to provide a control signal. The switching network includes the voltage node and is configured to operate in a first condition or in a second condition based on the control signal. Based on the first condition, the voltage node is configured to have a voltage value increase to the first voltage value.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Jaw-Juinn HORNG, Szu-Lin LIU, Chung-Hui CHEN
  • TEMPERATURE/VOLTAGE DETECTION CIRCUIT
    Publication number: 20140368264
    Abstract: A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal.
    Type: Application
    Filed: February 28, 2014
    Publication date: December 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn HORNG, Szu-Lin LIU, Chung-Hui CHEN
  • INTEGRATED CIRCUIT HAVING SHIELDING STRUCTURE
    Publication number: 20140327119
    Abstract: An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first metallization layer. Each shielding structure includes a plurality of non-contiguous shielding patterns aligned along the first direction. The plurality of shielding structures includes a first and a second shielding structures in a second metallization layer that adjoins the first metallization layer and a third and a fourth shielding structures in a third metallization layer that adjoins the first metallization layer. The first metallization layer is between the second and the third metallization layers. The first and the second shielding structures are separated from each other along a second direction perpendicular to the first direction. The third and the fourth shielding structures are separated from each other along the second direction.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventor: Chung-Hui CHEN
  • Low power/high speed TSV interface design
    Patent number: 8878369
    Abstract: A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Hui Chen, Jaw-Juinn Horng, Shuo-Mao Chen, Der-Chyang Yeh
  • Semiconductor device feature density gradient verification
    Patent number: 8856707
    Abstract: A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Young-Chow Peng, Chung-Hui Chen, Chien-Hung Chen, Po-Zeng Kang
  • Decoupling capacitor and layout for the capacitor
    Patent number: 8847320
    Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui Chen
  • Method of and system for generating optimized semiconductor component layout
    Patent number: 8850379
    Abstract: A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Chen, Yung-Chow Peng, Chung-Hui Chen, Chih Ming Yang
  • GUARD STRUCTURE FOR SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING GUARD LAYOUT PATTERN FOR SEMICONDUCTOR LAYOUT PATTERN
    Publication number: 20140239450
    Abstract: A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn HORNG, Jen-Hao YEH, Fu-Chih YANG, Chung-Hui CHEN
  • Integrated circuits and fabrication methods thereof
    Patent number: 8803320
    Abstract: An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Hui Chen
  • DECOUPLING CAPACITOR AND METHOD OF MAKING SAME
    Publication number: 20140159195
    Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui CHEN
  • Device layout for reference and sensor circuits
    Patent number: 8736355
    Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn Horng, Chung-Hui Chen, Sun-Jay Chang, Chia-Hsin Hu
  • Level shifting circuit and semiconductor device using the same
    Patent number: 8704579
    Abstract: A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Hui Chen
  • Decoupling capacitor and method of making same
    Patent number: 8692306
    Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui Chen
  • DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING AND METHOD OF FORMING THE SAME
    Publication number: 20140077331
    Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hsin HU, Sun-Jay CHANG, Jaw-Juinn HORNG, Chung-Hui CHEN
  • DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS
    Publication number: 20140077230
    Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn HORNG, Chung-Hui CHEN, Sun-Jay CHANG, Chia-Hsin HU
  • THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT
    Publication number: 20140008817
    Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
    Type: Application
    Filed: September 12, 2013
    Publication date: January 9, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jaw-Juinn HORNG, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
  • SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION
    Publication number: 20130346935
    Abstract: A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
    Type: Application
    Filed: August 28, 2013
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Young-Chow PENG, Chung-Hui Chen, Chien-Hung Chen, Po-Zeng Kang