Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

Abstract: A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

Abstract: An antifuse element includes a conductive region formed in a semiconductor substrate extending in a first direction, a dielectric layer formed on a portion of the conductive region, a first conductive plug formed on the dielectric layer, a second conductive plug formed on another portion of the conductive region, a first conductive member formed over the first conductive plug, and a second conductive member formed over the second conductive plug. The dielectric layer has a first dielectric portion extending in a second direction, and a second dielectric portion extending in the first direction, in which the dielectric layer implements an electrical isolation between the conductive region and the first conductive plug. The first conductive plug has a first region of a first width and a second region of a second width, and the first width is greater than the second width.

Abstract: An antifuse element includes a conductive region formed in a semiconductor substrate extending in a first direction, a dielectric layer formed on a portion of the conductive region, a first conductive plug formed on the dielectric layer, a second conductive plug formed on another portion of the conductive region, a first conductive member formed over the first conductive plug, and a second conductive member formed over the second conductive plug. The dielectric layer has a first dielectric portion extending in a second direction, and a second dielectric portion extending in the first direction, in which the dielectric layer implements an electrical isolation between the conductive region and the first conductive plug. The first conductive plug has a first region of a first width and a second region of a second width, and the first width is greater than the second width.

Abstract: The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor layer, and a contact. The semiconductor layer is over the semiconductor substrate. The contact has an interface with the semiconductor layer. The contact is substantially tapered toward the semiconductor substrate to the interface.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive layer. The semiconductor substrate has a plurality of mesas. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the mesas, respectively. The barrier layer is formed over a first lateral surface of the mesa, a second lateral surface of the block, an upper surface of the semiconductor substrate adjacent to the first lateral surface, and a front surface of the dielectric layer adjacent to the second lateral surface. The conductive layer has a base and a plurality of protrusions extending from the base and in contact with the barrier layer disposed over the upper surface, the first lateral surface, and the second lateral surface. A grain size of the base and the protrusions is consistent.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor layer, and a contact. The semiconductor layer is over the semiconductor substrate. The contact has an interface with the semiconductor layer. The contact is substantially tapered toward the semiconductor substrate to the interface.

Abstract: The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.

Abstract: The present disclosure provides a semiconductor manufacturing apparatus for processing a semiconductor subject. The semiconductor manufacturing apparatus includes a processing chamber, a first electrode, a second electrode, an RF power supply, and one or more light generators. The first electrode is disposed within the processing chamber. The second electrode is disposed within the processing chamber and substantially beneath the first electrode. The RF power supply is electrically connected to the first electrode. The one or more light generators are disposed within the processing chamber for irradiating the semiconductor subject, thereby releasing charges from the semiconductor subject.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive layer. The semiconductor substrate has a plurality of mesas. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the mesas, respectively. The barrier layer is formed over a first lateral surface of the mesa, a second lateral surface of the block, an upper surface of the semiconductor substrate adjacent to the first lateral surface, and a front surface of the dielectric layer adjacent to the second lateral surface. The conductive layer has a base and a plurality of protrusions extending from the base and in contact with the barrier layer disposed over the upper surface, the first lateral surface, and the second lateral surface. A grain size of the base and the protrusions is consistent.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, and silicide layer. The semiconductor substrate has a plurality of protrusions. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the protrusions. The silicide layer is disposed over a first sidewall of the protrusions, a second sidewall of the blocks, and an upper surface of the semiconductor substrate adjacent to the first sidewall, and a bottom surface of the silicide layer is lower than a first surface of the semiconductor substrate. The present disclosure further provides a method for manufacturing the semiconductor structure.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a plurality of first isolation structures disposed on the substrate, and a plurality of first semiconductor islands disposed on the substrate and separated from each other by the plurality of first isolation structures. In some embodiments, each of the plurality of first isolation structures includes a first bottom surface in contact with the substrate and a first top surface opposite to the first bottom surface. In some embodiments, a width of the first bottom surface is greater than a width of the first top surface.

Abstract: The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.

Abstract: A surface-mount piezoelectric sensor applied to logistics for real-time monitoring is provided. The piezoelectric sensor includes a flexible substrate in the form of a cross and a conductive line formed on the flexible substrate. A plurality of sensing members corresponding in number to end faces of a packaging box is adhered to the conductive line. The cross-shaped piezoelectric sensor is placed at the bottom of the packaging box, and the sensing members of the piezoelectric sensors are bonded to the respective end faces of the packaging box by means of a turnover operation, thereby simplifying the operation process and providing an all-round monitoring effect.