Patents by Inventor Chung-Yen Chou
Chung-Yen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12178144Abstract: An integrated chip comprising a memory cell is provided. The memory cell is disposed over a substrate and comprises a data storage layer between a top metal layer and a bottom metal layer. An etch stop layer overlies the top metal layer. An upper dielectric layer overlies the etch stop layer. Outer sidewalls of the etch stop layer, outer sidewalls of the upper dielectric layer, and outer sidewalls of the top metal layer are aligned. A top electrode overlies the memory cell. The top electrode directly contacts inner sidewalls of the top metal layer, inner sidewalls of the etch stop layer, and inner sidewalls of the upper dielectric layer.Type: GrantFiled: July 31, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Yen Chou
-
Patent number: 12094720Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.Type: GrantFiled: September 8, 2021Date of Patent: September 17, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chung-Yen Chou
-
Patent number: 12069851Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.Type: GrantFiled: March 17, 2020Date of Patent: August 20, 2024Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chung-Yen Chou, Chih-Yuan Chen, Qinfu Zhang, Chao-Wei Lin, Chia-Yi Chu, Jen-Chieh Cheng, Jen-Kuo Wu, Huixian Lai
-
Patent number: 12040269Abstract: The present application relates to a preparation method for leads of semiconductor structure and semiconductor structure. The preparation method comprises: providing a substrate covered with a conductive layer, the substrate having a first region and a second region being connected with the first region at side surfaces; sequentially forming, on the conductive layer, a second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other; etching the second dielectric layer for the first time; removing the mask layer in the first region; etching the second dielectric layer for the second time, forming, respectively in the first region and the second region, a first window and a second window; and etching the exposed conductive layer, forming leads comprising wide lines in the first region and narrow lines in the second region.Type: GrantFiled: March 15, 2021Date of Patent: July 16, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chung Yen Chou
-
Publication number: 20230380304Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventor: Chung-Yen Chou
-
Patent number: 11800818Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.Type: GrantFiled: July 9, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Yen Chou
-
Patent number: 11742262Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.Type: GrantFiled: April 19, 2021Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yuan-Tai Tseng, Chia-Shiung Tsai, Chung-Yen Chou, Ming-Chyi Liu
-
Publication number: 20230200254Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: CHUNG-YEN CHOU, FU-TING SUNG, YAO-WEN CHANG, SHIH-CHANG LIU
-
Publication number: 20230141117Abstract: The present application relates to a preparation method for leads of semiconductor structure and semiconductor structure. The preparation method comprises: providing a substrate covered with a conductive layer, the substrate having a first region and a second region being connected with the first region at side surfaces; sequentially forming, on the conductive layer, a second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other; etching the second dielectric layer for the first time; removing the mask layer in the first region; etching the second dielectric layer for the second time, forming, respectively in the first region and the second region, a first window and a second window; and etching the exposed conductive layer, forming leads comprising wide lines in the first region and narrow lines in the second region.Type: ApplicationFiled: March 15, 2021Publication date: May 11, 2023Inventor: Chung Yen Chou
-
Patent number: 11581484Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.Type: GrantFiled: August 3, 2021Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu
-
Publication number: 20220044940Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.Type: ApplicationFiled: September 8, 2021Publication date: February 10, 2022Inventor: CHUNG-YEN CHOU
-
Publication number: 20220028730Abstract: A semiconductor structure and a method for manufacturing the same are provided. The manufacturing method includes: providing a semiconductor substrate having trench isolation layers and a plurality of active areas; removing a preset thickness of the trench isolation layers to form a plurality of openings which expose the upper parts of the active areas; forming additional layers on side walls of the exposed upper parts of the active areas; and forming filling isolation layers in the openings to fill the openings, the filling isolation layers and the retained trench isolation layers together constituting first shallow trench isolation structures.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Inventor: Chung Yen Chou
-
Publication number: 20220028867Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.Type: ApplicationFiled: March 17, 2020Publication date: January 27, 2022Inventors: Chung-Yen CHOU, Chih-Yuan CHEN, Qinfu ZHANG, Chao-Wei LIN, Chia-Yi CHU, Jen-Chieh CHENG, Jen-Kuo WU, Huixian LAI
-
Patent number: 11233145Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.Type: GrantFiled: April 10, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
-
Publication number: 20210367145Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: CHUNG-YEN CHOU, FU-TING SUNG, YAO-WEN CHANG, SHIH-CHANG LIU
-
Publication number: 20210351349Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.Type: ApplicationFiled: July 9, 2021Publication date: November 11, 2021Inventor: Chung-Yen Chou
-
Patent number: 11167979Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.Type: GrantFiled: November 13, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Yen Chou
-
Patent number: 11167982Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.Type: GrantFiled: June 15, 2020Date of Patent: November 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai, Ru-Liang Lee
-
Patent number: 11145593Abstract: A method of manufacturing a semiconductor structure includes: providing a substrate; forming a first conductive layer having a first opening over the substrate; depositing a first dielectric layer over the first conductive layer and covering the first opening; forming a second conductive layer having a second opening over the first dielectric layer; depositing a second dielectric layer over the second conductive layer and covering the second opening; performing an etching operation through the second dielectric layer at the second opening and the first dielectric layer at the first opening to form a first via; and forming a first conductive structure in the first via.Type: GrantFiled: July 3, 2020Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chung-Yen Chou
-
Patent number: 11143817Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate and a gate element over the substrate. The gate element includes: a gate dielectric layer over the substrate; a gate electrode over the gate dielectric layer; and a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode. A manufacturing method of the same is also disclosed.Type: GrantFiled: November 13, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Chang Chang, Chung-Yen Chou, Ming-Chyi Liu, Shih-Chang Liu