Abstract: A position-adjustable probing device comprises a stationary probe comprising a first coaxial structure having a first needle core, a first dielectric layer, and a first exterior conductive layer, and a first and a second movable probes. The first movable probe arranged at a first side of the stationary probe comprises a ground needle core, and a first extending structure comprising a first planar structure electrically contacted with the stationary probe through a first movement, a first top surface and a first bottom surface. The second movable probe arranged at a second side of the stationary needle comprises a second coaxial structure comprising a second needle core, a second dielectric layer, and a second exterior conductive layer, and a second extending structure comprising a second planar structure electrically contacted with the stationary probe through a second movement, a second top surface, and a second bottom surface.

Abstract: A positioning system based on street view information for a vehicle is provided. The positioning system includes a database, an image capturing module and a processing circuit. The database includes information of a plurality of identifiable objects with high discrimination and location information of the plurality of identifiable objects. The image capturing module is disposed on the vehicle and configured to capturing a current image. The processing circuit is configured to determine whether at least one current identifiable object in the current image matches at least one of the plurality of identifiable objects with high discrimination.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.

Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.

Abstract: The present application relates to a preparation method for leads of semiconductor structure and semiconductor structure. The preparation method comprises: providing a substrate covered with a conductive layer, the substrate having a first region and a second region being connected with the first region at side surfaces; sequentially forming, on the conductive layer, a second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other; etching the second dielectric layer for the first time; removing the mask layer in the first region; etching the second dielectric layer for the second time, forming, respectively in the first region and the second region, a first window and a second window; and etching the exposed conductive layer, forming leads comprising wide lines in the first region and narrow lines in the second region.

Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.

Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: The present application relates to a preparation method for leads of semiconductor structure and semiconductor structure. The preparation method comprises: providing a substrate covered with a conductive layer, the substrate having a first region and a second region being connected with the first region at side surfaces; sequentially forming, on the conductive layer, a second dielectric layer, a first dielectric layer and a mask layer which are superposed one upon the other; etching the second dielectric layer for the first time; removing the mask layer in the first region; etching the second dielectric layer for the second time, forming, respectively in the first region and the second region, a first window and a second window; and etching the exposed conductive layer, forming leads comprising wide lines in the first region and narrow lines in the second region.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The manufacturing method includes: providing a semiconductor substrate having trench isolation layers and a plurality of active areas; removing a preset thickness of the trench isolation layers to form a plurality of openings which expose the upper parts of the active areas; forming additional layers on side walls of the exposed upper parts of the active areas; and forming filling isolation layers in the openings to fill the openings, the filling isolation layers and the retained trench isolation layers together constituting first shallow trench isolation structures.

Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

Abstract: A method of manufacturing a semiconductor structure includes: providing a substrate; forming a first conductive layer having a first opening over the substrate; depositing a first dielectric layer over the first conductive layer and covering the first opening; forming a second conductive layer having a second opening over the first dielectric layer; depositing a second dielectric layer over the second conductive layer and covering the second opening; performing an etching operation through the second dielectric layer at the second opening and the first dielectric layer at the first opening to form a first via; and forming a first conductive structure in the first via.