Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with a sensing well having one or more sensing well spacers that reduce a size of the sensing well after its formation. In some embodiments, the integrated bio-sensor has a sensing device disposed within a semiconductor substrate. A dielectric structure is disposed onto a first side of the semiconductor substrate. The dielectric structure has an opening with a first width, which is exposed to an ambient environment and that overlies the sensing device. One or more sensing well spacers are arranged on sidewalls of the opening. The one or more sensing well spacers expose a bottom surface of the opening to define a sensing well having a second width that is smaller than the first width.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.

Abstract: An inductor structure is provided. The inductor structure includes a first dielectric layer formed over a substrate and a first metal layer formed in the first dielectric layer. The inductor structure includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a main portion and a tapered portion extending from the main portion.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a planar bottom barrier layer over and in contact with the Nth metal layer, a data storage layer over the planar bottom barrier layer, an electrode over the data storage layer, and an (N+1)th metal layer over the electrode. N is a positive integer. A manufacturing method for the semiconductor structure is also provided.

Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first opening in the first etch stop layer and the first dielectric layer. The method further comprises filling the first opening with a conductive material. The method additionally comprises forming a second etch stop layer and a second dielectric layer over the first etch stop layer. The method further comprises forming a second opening to expose the conductive material. The method additionally comprises forming a capacitor in the second opening and in contact with the conductive material.

Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.

Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Abstract: The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask.

Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.

Abstract: The present disclosure relates to integrated circuits having a resistive random access memory (RRAM) cell, and associated methods of forming such RRAM cells. In some embodiments, the RRAM cell includes a bottom electrode and a top electrode which are separated from one another by an RRAM dielectric. A bottom electrode sidewall and a top electrode sidewall are vertically aligned to one another, and an RRAM dielectric sidewall is recessed back from the bottom electrode sidewall and the top electrode sidewall.

Abstract: A microelectromechanical systems (MEMS) structure with a cavity hermetically sealed using a mask layer is provided. A capping substrate is arranged over a MEMS substrate, which includes a movable element. The capping substrate includes the cavity arranged over and opening to the movable element, and includes a seal opening in fluid communication with the cavity. The mask layer is arranged over the capping substrate. The mask layer overhangs the seal opening and laterally surrounds a mask opening arranged over the seal opening. A seal layer is arranged over the mask layer and the mask opening. The seal layer is configured to hermetically seal the cavity. A method for manufacturing the MEMS structure is also provided.

Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.

Abstract: A method for performing a high aspect ratio etch is provided. A semiconductor substrate is provided with a hard mask layer arranged over the semiconductor substrate. A first etch is performed into the hard mask layer to form a hard mask opening exposing the semiconductor substrate. The hard mask opening has a bottom width. A second etch is performed into the semiconductor substrate, through the hard mask opening, to form a substrate opening with a top width that is about equal to the bottom width of the hard mask opening. A protective layer is formed lining a sidewall of the substrate opening. A third etch is performed into the semiconductor substrate, through the hard mask opening, to increase a height of the substrate opening. The top width of the substrate opening remains substantially unchanged during the third etch. A semiconductor structure with a high aspect ratio opening is also provided.