Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: A laser slicing apparatus, in which a laser module provides a laser beam, and a light splitting element of a focusing lens set splits the laser beam into a plurality of focused laser beams to form a plurality of induce lines having first laser modified cracks in a modified layer at a predetermined depth inside a substrate. A rotating module rotates the light splitting element with an angle, and the light splitting element converts the focused laser beams according to this angle to form a plurality of modified groups between the induce lines. Each modified group includes a plurality of modified lines having second laser modified cracks, and the first laser modified cracks and the second laser modified cracks are connected to each other to form a continuous laser modified crack in the modified layer at the predetermined depth inside the substrate, thereby speeding up the laser slicing production.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.

Abstract: A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate. The opening portion of the substrate is under the diaphragm, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a pillar structure connected with the backplate and the diaphragm and a protection post structure extending from the backplate into the air gap. From a top view of the backplate, the protection post structure surrounds the pillar structure.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first microstructures, and a high-k dielectric material between the first microstructures and the second microstructures.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A semiconductor structure comprises: a semiconductor substrate; one or more first implant layers disposed in the semiconductor substrate and forming a circuit portion and a first test portion, the circuit portion forming an at least partially formed semiconductor circuit; and one or more second implant layers disposed in the semiconductor substrate and further forming the circuit portion and a second test portion, wherein the first and second test portions are spaced apart. A first implantation profile of the one or more first implant layers of the first test portion is obtained during a testing procedure, and the first implantation profile is a representation of a second implantation profile of the one or more first implant layers of the circuit portion.

Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device for an image detection system that is used in a low-light environment. The complementary metal-oxide semiconductor image sensor device includes a photodiode for detecting near infrared and/or short-wave infrared light waves. The photodiode includes a layer of a quantum dot material and a transparent electrode over the layer of the quantum dot material. In addition to the photodiode having an improved quantum efficiency relative to a silicon-based photodiode, the photodiode is integrated within a color filter array structure to obviate the need for separate a separate visible light complementary metal-oxide semiconductor image sensor device in the image detection system.

Abstract: Some implementations described herein include an optoelectronic device for a low-lighting application and techniques to form the optoelectronic device. The optoelectronic device includes near infrared light emitting diodes, near infrared photodiodes, and visible light photodiodes combined in a single substrate. The near infrared light emitting diodes and the near infrared photodiodes are formed using a selectively grown epitaxial material. The selectively grown epitaxial material (e.g., silicon germanium, gallium arsenide, or another type III/V material) improves a quantum efficiency performance of the near infrared photodiode relative to another photodiode that may be formed through doping a silicon material.

Abstract: An electronic device and a method of transmitting USB commands are provided. The method includes: (A) allocating a buffer area in a memory; (B) receiving a USB command; (C) retrieving control transfer information of the USB command; (D) storing the control transfer information in the buffer area; (E) repeating steps (B) to (D) until a condition for ending a control aggregation is met; (F) generating an aggregated USB command according to the content of the buffer area; and (G) transmitting the aggregated USB command.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A processor chip includes a logic circuit. The logic circuit is configured to be coupled to an electronic device. A configuration of the logic circuit corresponds to a plurality of candidate configurations. The configuration of the logic circuit is switched among the candidate configurations, and the electronic device associates with the processor chip to implement a function corresponding to the configuration of the logic circuit. When the configuration of the logic circuit is a first configuration and the electronic device executes a first driver program, the function is a first network-connection function. When the configuration of the logic circuit is a second configuration and the electronic device executes a second driver program, the function is a second network-connection function different from the first network-connection function.

Abstract: A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Abstract: Dynamic management method and system for an active state power management (ASPM) mechanism are provided. The method is applicable to a peripheral component interconnect express (PCIe) transmission architecture that includes a host and a PCIe downstream component. The method includes: configuring the PCIe downstream component to perform: determining whether data transmission status between a PCIe upstream component and the PCIe downstream component is in a busy state, a stable idle state or a temporary state; in response to determining that the data transmission status is in the busy state, forcibly disabling the ASPM function; in response to determining that the data transmission state is in the stable idle state, forcibly enabling the ASPM function; and in response to determining that the data transmission state is in the temporary state, determining whether the data transmission state is the busy state, the stable idle state or the temporary state again.