Abstract: A liner for an isolation structure is formed in a device layer of a semiconductor device using one or more high dielectric constant (high-k) dielectric materials. The high-k dielectric material(s) of the liner have a dielectric constant that is greater than the dielectric constant of silicon nitride (SixNy), which enables increased passivation to be achieved for the isolation, and enables reduced current leakage to be achieved for integrated circuit structures in the device layer. The isolation structure and/or the liner may be formed by processes that are compatible with subsequent layers and/or structures that are to be formed in the semiconductor device.

Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip, a conductive plug, and a dielectric structure surrounding a portion of the sidewall of the conductive plug. The conductive plug extends from the first semiconductor chip to the second semiconductor chip for electrically connecting the first metallization structure and the second metallization structure. The dielectric structure includes a middle dielectric layer between an outer dielectric layer and an inner dielectric layer. The outer dielectric layer is formed between the first substrate and the middle dielectric layer. The dielectric constant of the outer dielectric layer is greater than the dielectric constant of the middle dielectric layer.

Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.

Abstract: A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

Abstract: A method for generating power-compensation values with historical data association and a wireless communication module are provided. In the method, historical data of associations among the power-compensation values for multiple frequencies that the wireless communication module operates on are obtained. Summations of multiple values of associations among the power-compensation values in multiple frequencies are calculated, and a largest summation of the values of associations is used to decide a critical frequency. The multiple values of associations between the power-compensation value of the critical frequency and the power-compensation values of the multiple frequencies form a dataset. The power-compensation values appropriate to the multiple frequencies can be estimated based on the power-compensation value of the critical frequency with reference to the values of associations among the multiple frequencies. A power-compensation list written into a memory is formed.

Abstract: A method for obtaining power compensation values with statistical data and a wireless communication module are provided. The wireless communication module includes a wireless communication circuit that transmits wireless radio-frequency signals with a transmitting power, and a memory used to store a set of power-compensation values that are obtained using statistical data under multiple frequencies. In the method, the statistical data of the power-compensation values under multiple frequencies for the multiple wireless communication modules is obtained, data characteristics of the statistical data is referred to for estimating a power-compensation value corresponding to each frequency of the wireless communication module. Then, the multiple power-compensation values are written into the memory of the wireless communication module.

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first microstructures, and a high-k dielectric material between the first microstructures and the second microstructures.

Abstract: A pneumatic control nozzle assembly, a substrate processing device and a control method thereof are provided. The pneumatic control nozzle assembly includes a nozzle body, a closed movable element, and a pneumatic driving part. The nozzle body includes an inlet end, an outlet end, and an internal channel. The closed movable element is movably disposed in the internal channel of the nozzle body. The pneumatic driving part is connected to the nozzle body and the closed movable element, and is configured to drive the closed movable element to perform a linear movement in the internal channel so that the nozzle body changes between an open state and a closed state. When the nozzle body is in the closed state, the closed movable element plugs the outlet end located at an end of the nozzle body.

Abstract: Dynamic management method and system for an active state power management (ASPM) mechanism are provided. The method is applicable to a peripheral component interconnect express (PCIe) transmission architecture that includes a host and a PCIe downstream component. The method includes: configuring the PCIe downstream component to perform: determining whether data transmission status between a PCIe upstream component and the PCIe downstream component is in a busy state, a stable idle state or a temporary state; in response to determining that the data transmission status is in the busy state, forcibly disabling the ASPM function; in response to determining that the data transmission state is in the stable idle state, forcibly enabling the ASPM function; and in response to determining that the data transmission state is in the temporary state, determining whether the data transmission state is the busy state, the stable idle state or the temporary state again.

Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor substrate and forming a plurality of first metal lines extending along a first direction in the first semiconductor substrate. Each of the plurality of first metal lines includes a plurality of first discrete portions spaced along the first direction. The method further includes providing a second semiconductor substrate, and forming a second metal line below each of the plurality of first metal lines and extending along the first direction in the second semiconductor substrate. The second metal line includes a plurality of second discrete portions spaced along the first direction and the plurality of second discrete portions and the plurality of first discrete portions are alternately staggered along the first direction. The method also includes forming a bonding connector connecting the plurality of second discrete portions to a corresponding first metal line of the plurality of first metal lines.

Abstract: A semiconductor chip includes a first chip feature, and a second chip feature disposed on the first chip feature. The first chip feature includes a first substrate, a first seal ring disposed on the first substrate, a second seal ring disposed on the first substrate, and a first dielectric structure surrounding the first and second seal rings. The second chip feature includes a second substrate, a third seal ring disposed below the second substrate and connected to the first seal ring, a second dielectric structure surrounding the third seal ring, and a conductive ring formed in the second substrate and connected to the third seal ring. The second seal ring, a combination of the first and third seal rings, and a portion of the first dielectric structure and a portion of the second dielectric structure that are disposed between the second seal ring and the combination cooperatively constitute a capacitor.

Abstract: A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Abstract: A spraying device, a spraying system, and an operating method thereof for a semiconductor substrate are provided. The spraying device includes a main channel and at least one branch channel. The main channel has a main channel inlet and a main channel outlet provided for gas to flow from the main channel inlet to the main channel outlet. The at least one branch channel is communicated with the main channel, and each of the at least one branch channel has a branch channel inlet provided for fluid to flow from the branch channel inlet to the main channel outlet.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die bonded together such that the first semiconductor die and the second semiconductor die are stacked or vertically arranged in the semiconductor package. A seal ring region is provided around the device regions of the first semiconductor die and the second semiconductor die. To prevent, minimize, and/or reduce the likelihood of electrical leakage propagating between the first and second semiconductor dies through the seal ring region, one or more through-substrate isolation structures are included through a substrate of the first semiconductor die and/or through a substrate of the second semiconductor die in the seal ring region.

Abstract: An elongated conductive structure is included through a device layer of a semiconductor die included in a semiconductor die package. The elongated conductive structure connects to metallization layers in the interconnect structures on opposing sides of the device layer. To prevent, minimize, and/or reduce current leakage from the elongated conductive structure, one or more liners may be included between the elongated conductive structure and the device layer. The one or more liners include a high dielectric constant (high-k) dielectric liner. The high-k dielectric liner provides increased electrical isolation compared to other types of dielectric liners. In this way, the high-k dielectric liner enables increased electrical isolation, in addition to providing surface passivation and/or metal diffusion blocking, to be achieved.

Abstract: An image sensor device may include one or more types of antireflection structures on a metal grid surrounding the pixel sensors in a pixel sensor array of the image sensor device. The antireflection structures may include an antireflective layer, nanostructures extending from the antireflective layer, and/or a plurality of cavities formed in the metal grid structure. The antireflection structures may be included in and/or on one or more surfaces of the metal grid structure to reduce the reflection of incident light, which may reduce the likelihood and/or magnitude of optical crosstalk between adjacent pixel sensors in the pixel sensor array.

Abstract: Autofocus functionality is integrated into a pixel sensor array of an image sensor device described herein by including autofocus pixel sensors with imaging pixel sensors in the pixel sensor array. A metal grid structure may be included around the autofocus pixel sensors and the imaging pixel sensors in the pixel sensor array. Grid extensions of the metal grid structure extend laterally outward over at least a portion of photodiodes of the autofocus pixel sensors, thereby shielding the portions of the photodiodes from incident light. The autofocus pixel sensors may be arranged in pairs in the pixel sensor array such that opposing sides of the photodiodes of the autofocus pixel sensors in a pair are shielded by grid extensions. This results in a phase difference between the incident light sensed by the autofocus pixel sensors in the pair, which may be used for determining the focus of the pixel sensor array.

Abstract: A data receiving and transmitting method includes following steps: receiving and transmitting a plurality of general priority data by a first request block; receiving and transmitting a plurality of high priority data by a second request block; and if the first request block is unable to receive and transmit a portion data of the plurality of general priority data, receiving and transmitting the portion data of the plurality of general priority data by the second request block.

Abstract: A semiconductor package structure includes a first semiconductor component, a second semiconductor component, a bonded structure, a first through-substrate via, a pad, and a conductive feature. The first semiconductor component includes a first substrate and a first interconnect structure electrically connecting the first through-substrate via to the pad. The first interconnect structure is disposed over a first side of the first substrate. The second semiconductor component includes a second substrate and a second interconnect structure. The first through-substrate via penetrates the first substrate from a second side to the first side. The second side is opposite to the first side. The pad is disposed over the second side of the first substrate. The conductive feature is disposed over the second side of the first substrate and between the first through-substrate via and the pad. The conductive feature is electrically connected to the first interconnect structure by the first through-substrate via.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.