Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A power supply phase doubling system includes a pulse width modulation (PWM) controller and first and second phase doubling chips. The PWM controller outputs a PWM signal. The first phase doubling chip is operated at a power supply voltage and has a first PWM output pin to generate a first control signal and a second control signal according to the PWM signal, and generates a first output signal according to the first control signal. The second phase doubling chip is operated at the power supply voltage, has a second PWM output pin, and is configured to generate a second output signal according to the second control signal. The first and second phase doubling chips are respectively switched between a master mode and a slave mode according to a voltage level of the first PWM output pin and a voltage level of the second PWM output pin.

Abstract: A neutron capture therapy system and a target material for a particle beam generation apparatus, the heat dissipation performance of a target material might be improved. A neutron capture therapy system includes a neutron generation apparatus and a beam shaping body, the neutron generation apparatus includes an accelerator and a target material, and a charged particle beam generated by means of acceleration of the accelerator acts with the target material to generate a neutron beam. The target material includes an active layer, an anti-foaming layer, a heat dissipation layer and a heat conduction layer, the active layer acts with a charged particle beam to generate a neutron beam; the anti-foaming layer suppresses foaming caused by the charged particle beam; the heat dissipation layer directly and rapidly conducts to the heat conduction layer, heat deposited on the active layer, and discharges by means of a cooling medium.

Abstract: A method of detecting electromagnetic radiation includes illuminating a photodiode of a pixel sensor with electromagnetic radiation, using vertical gate structures of a transfer transistor to couple a cathode of the photodiode to an internal node of the pixel sensor, thereby generating an internal node voltage level, and generating an output voltage level of the pixel sensor based on the internal node voltage level.

Abstract: A voltage detection device is provided. The voltage detection device includes a first voltage divider circuit, a comparison circuit, and a second voltage divider circuit. The first voltage divider circuit is configured to receive an input voltage and output a comparison voltage according to the input voltage. The comparison circuit is configured to receive the comparison voltage to compare the comparison voltage with a reference voltage and determine whether to change a trigger signal according to a comparison result. The second voltage divider circuit is configured to receive the input voltage. When the input voltage is greater than or equal to a predetermined voltage value, the second voltage divider circuit and the first voltage dividing circuit form a parallel structure to pull down the comparison voltage.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure located on the substrate, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, a plurality of contact portions disposed between the first type semiconductor structure and the substrate, and a first conductive oxide layer, a second conductive oxide layer, a first insulating layer and a second insulating layer. The plurality of contact portions is separated from each other, and one of them includes a semiconductor and has a side wall. The first conductive oxide layer contacts the contact portion, and the second conductive oxide layer contacts the first conductive oxide layer. The first insulating layer contacts the side wall. The second insulating layer is disposed between the first insulating layer and the second conductive oxide layer.

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first microstructures, and a high-k dielectric material between the first microstructures and the second microstructures.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A semiconductor structure comprises: a semiconductor substrate; one or more first implant layers disposed in the semiconductor substrate and forming a circuit portion and a first test portion, the circuit portion forming an at least partially formed semiconductor circuit; and one or more second implant layers disposed in the semiconductor substrate and further forming the circuit portion and a second test portion, wherein the first and second test portions are spaced apart. A first implantation profile of the one or more first implant layers of the first test portion is obtained during a testing procedure, and the first implantation profile is a representation of a second implantation profile of the one or more first implant layers of the circuit portion.

Abstract: Some implementations described herein include a complementary metal oxide semiconductor image sensor device for an image detection system that is used in a low-light environment. The complementary metal-oxide semiconductor image sensor device includes a photodiode for detecting near infrared and/or short-wave infrared light waves. The photodiode includes a layer of a quantum dot material and a transparent electrode over the layer of the quantum dot material. In addition to the photodiode having an improved quantum efficiency relative to a silicon-based photodiode, the photodiode is integrated within a color filter array structure to obviate the need for separate a separate visible light complementary metal-oxide semiconductor image sensor device in the image detection system.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: Some implementations described herein include an optoelectronic device for a low-lighting application and techniques to form the optoelectronic device. The optoelectronic device includes near infrared light emitting diodes, near infrared photodiodes, and visible light photodiodes combined in a single substrate. The near infrared light emitting diodes and the near infrared photodiodes are formed using a selectively grown epitaxial material. The selectively grown epitaxial material (e.g., silicon germanium, gallium arsenide, or another type III/V material) improves a quantum efficiency performance of the near infrared photodiode relative to another photodiode that may be formed through doping a silicon material.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Abstract: An electronic device and a method of transmitting USB commands are provided. The method includes: (A) allocating a buffer area in a memory; (B) receiving a USB command; (C) retrieving control transfer information of the USB command; (D) storing the control transfer information in the buffer area; (E) repeating steps (B) to (D) until a condition for ending a control aggregation is met; (F) generating an aggregated USB command according to the content of the buffer area; and (G) transmitting the aggregated USB command.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.