Patents by Inventor Chyi-Tsong Ni
Chyi-Tsong Ni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145561Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Hong-Ming LO, Chun-Chih LIN, Chyi-Tsong NI
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Patent number: 11938521Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.Type: GrantFiled: February 2, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuang-Wei Cheng, Cheng-Lung Wu, Chyi-Tsong Ni
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Publication number: 20240087935Abstract: A closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (FFU) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. The gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the FFU inlet. This enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. The closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Jyh-Shiou HSU, Chyi-Tsong NI, Mu-Tsang LIN, Su-Horng LIN
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Publication number: 20240084454Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Yung-Tsun LIU, Kuang-Wei CHENG, Sheng-chun YANG, Chih-Tsung LEE, Chyi-Tsong NI
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Patent number: 11929267Abstract: An ultraviolet (UV) lamp assembly of a UV curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. The UV lamp assembly includes: a UV lamp which emits UV light; a first reflector arranged proximate to a first side of the UV lamp, the first reflector including a first surface facing the UV lamp from which UV light emitted by the UV lamp is at least partially reflected; and a UV reflective coating partially coating the first surface of the reflector. Suitably, a plurality of areas of the first surface of the reflector remain uncoated with the UV reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to UV irradiation.Type: GrantFiled: August 17, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chun Hu, Kuang-Wei Cheng, Chyi-Tsong Ni
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Publication number: 20240063035Abstract: An ultraviolet (UV) lamp assembly of a UV curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. The UV lamp assembly includes: a UV lamp which emits UV light; a first reflector arranged proximate to a first side of the UV lamp, the first reflector including a first surface facing the UV lamp from which UV light emitted by the UV lamp is at least partially reflected; and a UV reflective coating partially coating the first surface of the reflector. Suitably, a plurality of areas of the first surface of the reflector remain uncoated with the UV reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to UV irradiation.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Inventors: Chien-Chun Hu, Kuang-Wei Cheng, Chyi-Tsong Ni
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Patent number: 11908909Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.Type: GrantFiled: July 29, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Hong-Ming Lo, Chun-Chih Lin, Chyi-Tsong Ni
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Publication number: 20240001409Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.Type: ApplicationFiled: July 26, 2023Publication date: January 4, 2024Inventors: Kuang-Wei Cheng, Cheng-Lung Wu, Chyi-Tsong Ni
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Patent number: 11851761Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.Type: GrantFiled: April 16, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Tsun Liu, Kuang-Wei Cheng, Sheng-chun Yang, Chih-Tsung Lee, Chyi-Tsong Ni
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Patent number: 11854851Abstract: A closed gas circulation system may include a sealed plenum, circulation fans, and a fan filter unit (FFU) inlet to contain, filter, condition, and re-circulate a gas through a chamber of an interface tool. The gas provided to the chamber is maintained in a conditioned environment in the closed gas circulation system as opposed to introducing external air into the chamber through the FFU inlet. This enables precise control over the relative humidity and oxygen concentration of the gas used in the chamber, which reduces the oxidation of semiconductor wafers that are transferred through the chamber. The closed gas circulation system may also include an air-flow rectifier, a return vent, and one or more vacuum pumps to form a downflow of collimated gas in the chamber and to automatically control the feed-forward pressure and flow of gas through the chamber and the sealed plenum.Type: GrantFiled: March 5, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyh-Shiou Hsu, Chyi-Tsong Ni, Mu-Tsang Lin, Su-Horng Lin
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Publication number: 20230402427Abstract: A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.Type: ApplicationFiled: August 10, 2023Publication date: December 14, 2023Inventors: Kuang-Wei CHENG, Chyi-Tsong NI
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Publication number: 20230375684Abstract: A target measurement device is provided. The target measurement device includes a fixing ring, a main body, and a transceiver. The fixing ring has a first surface. The main body is over the first surface of the fixing ring. The transceiver is coupled to the main body. The transceiver is at least movable between a center of the fixing ring to an edge of the fixing ring from a top view perspective. A method for measuring a target is also provided.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Inventors: PRADIP GIRDHAR CHAUDHARI, CHE-HUI LEE, CHIH-CHENG WEI, WEN-CHENG YANG, CHYI-TSONG NI
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Patent number: 11754691Abstract: A target measurement device is provided. The target measurement device includes a fixing ring, a main body, and a transceiver. The fixing ring has a first surface. The main body is over the first surface of the fixing ring. The transceiver is coupled to the main body. The transceiver is at least movable between a center of the fixing ring to an edge of the fixing ring from a top view perspective. A method for measuring a target is also provided.Type: GrantFiled: June 19, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pradip Girdhar Chaudhari, Che-Hui Lee, Chih-Cheng Wei, Wen-Cheng Yang, Chyi-Tsong Ni
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Publication number: 20230268227Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.Type: ApplicationFiled: April 27, 2023Publication date: August 24, 2023Inventors: Yu-Ting TSAI, Chung-Liang Cheng, Ching-Jing Wu, Chyi-Tsong Ni
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Patent number: 11735436Abstract: An apparatus for fabricating a semiconductor device has a housing defining a buffer chamber, a plurality of reactor ports formed in the housing for establishing interfaces with a plurality of process chambers that are to receive a wafer during a fabrication process to fabricate the semiconductor device, a wafer positioning robot positioned within the buffer chamber to transport the wafer between the plurality of process chambers through the plurality of reactor ports, a purge port formed in the housing for introducing a purge gas into the buffer chamber, a pump port formed in the housing for exhausting a portion of the purge gas from the buffer chamber, and a first flow enhancer that directs the purge gas flowing in an axial direction along a longitudinal axis of the purge port into the buffer chamber in a plurality of radial directions relative to the longitudinal axis.Type: GrantFiled: August 10, 2022Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chih-Tsung Lee, Sheng-Chun Yang, Yun-Tzu Chiu, Chao-Hung Wan, Yi-Ming Lin, Chyi-Tsong Ni
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Publication number: 20230257875Abstract: A method of fabricating semiconductor devices includes: loading one or more semiconductor wafers into a plurality of stations provided within a process chamber; applying a process to the semiconductor wafers which deposits a material on the one or more semiconductor wafers within the process chamber; and cleaning the process chamber. Suitably, cleaning the process chamber includes flowing a cleaning gas into the process chamber toward a deflector arranged in the process chamber, the deflector having a first surface upon which the flowed cleaning gas impinges, the first surface directing a first portion of the flowed cleaning gas impinging thereon in a first trajectory toward a first end of the process chamber and directing a second portion of the flowed cleaning gas impinging thereon in a second trajectory toward a second end of the process chamber, the second end being opposite the first end.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: Kuang-Wei Cheng, Sung-Ju Huang, Yung-Tsun Liu, Chih-Tsung Lee, Chyi-Tsong Ni
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Publication number: 20230257882Abstract: Methods and systems for chemical vapor deposition (CVD) are disclosed. The methods and systems use a showerhead including a domed internal baffle plate. The domed internal baffle plate is perforated. The presence of the domed internal baffle plate improves the uniformity of gas distribution through the holes of the showerhead across the surface area of the showerhead. This improves deposition uniformity on the semiconducting wafer substrate upon which CVD is being performed, or improves the cleaning of the reaction chamber when a cleaning gas is pumped in through the showerhead.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: Yung-Tsun Liu, Kuang-Wei Cheng, Sung-Ju Huang, Chih-Tsung Lee, Chyi-Tsong Ni
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Patent number: 11721662Abstract: A method of aligning two wafers during a bonding process includes aligning a first wafer having a plurality of alignment markings with a second wafer having a plurality of alignment markings. The method further includes placing a plurality of flags between the first wafer and the second wafer. The method further includes detecting movement of the plurality of flags with respect to the first wafer and the second wafer using at least one sensor. The method further includes determining whether the wafers remain aligned within an alignment tolerance based on the detected movement of the plurality of flags relative to the first wafer and the second wafer.Type: GrantFiled: November 4, 2020Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai Shih, Ching-Hou Su, Chyi-Tsong Ni, I-Shi Wang, Jeng-Hao Lin, Kuan-Ming Pan, Jui-Mu Cho, Wun-Kai Tsai
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Patent number: 11695150Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.Type: GrantFiled: August 19, 2021Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Su
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Patent number: 11670547Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.Type: GrantFiled: January 15, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Ching-Jing Wu, Chyi-Tsong Ni