Patents by Inventor Chyi-Tsong Ni

Chyi-Tsong Ni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12276024
    Abstract: Methods and systems for chemical vapor deposition (CVD) are disclosed. The methods and systems use a showerhead including a domed internal baffle plate. The domed internal baffle plate is perforated. The presence of the domed internal baffle plate improves the uniformity of gas distribution through the holes of the showerhead across the surface area of the showerhead. This improves deposition uniformity on the semiconducting wafer substrate upon which CVD is being performed, or improves the cleaning of the reaction chamber when a cleaning gas is pumped in through the showerhead.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Tsun Liu, Kuang-Wei Cheng, Sung-Ju Huang, Chih-Tsung Lee, Chyi-Tsong Ni
  • Publication number: 20250041906
    Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 6, 2025
    Inventors: Kuang-Wei Cheng, Cheng-Lung Wu, Chyi-Tsong Ni
  • Patent number: 12205921
    Abstract: A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Wei Cheng, Chyi-Tsong Ni
  • Patent number: 12194510
    Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuang-Wei Cheng, Cheng-Lung Wu, Chyi-Tsong Ni
  • Publication number: 20240384408
    Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Wen-Cheng CHENG, Che-Hung LIU, Yu-Cheng SHEN, Chyi-Tsong NI
  • Publication number: 20240387200
    Abstract: A chamber of a semiconductor fabrication facility may include a vent port diffuser. The vent port diffuser may include a first tube member configured to couple the vent port diffuser to a vent port of the chamber. The vent port diffuser may include a second tube member coupled to the first tube member. The second tube member may comprise a plurality of openings spaced along a length of the second tube member, with the plurality of openings configured to receive a fluid from the chamber. Based on the semiconductor fabrication facility including the vent port diffuser, the chamber may be configured to provide an improved flow field of a fluid within the chamber. In this way, the vent port diffuser may reduce defects of semiconductor devices transported through the chamber that might otherwise be caused by contaminants.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Yung-Tsun LIU, Chao-Hung WAN, Kuang-Wei CHENG, Chih-Tsung LEE, Chyi-Tsong NI
  • Publication number: 20240384416
    Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Yung-Tsun LIU, Kuang-Wei CHENG, Sheng-chun YANG, Chih-Tsung LEE, Chyi-Tsong NI
  • Publication number: 20240384414
    Abstract: Methods and systems for chemical vapor deposition (CVD) are disclosed. The methods and systems use a showerhead including a domed internal baffle plate. The domed internal baffle plate is perforated. The presence of the domed internal baffle plate improves the uniformity of gas distribution through the holes of the showerhead across the surface area of the showerhead. This improves deposition uniformity on the semiconducting wafer substrate upon which CVD is being performed, or improves the cleaning of the reaction chamber when a cleaning gas is pumped in through the showerhead.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Yung-Tsun Liu, Kuang-Wei Cheng, Sung-Ju Huang, Chih-Tsung Lee, Chyi-Tsong Ni
  • Publication number: 20240379471
    Abstract: A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 14, 2024
    Inventors: Kuang-Wei CHENG, Yung-Tsun LIU, Chih-Tsung LEE, Chyi-Tsong NI
  • Publication number: 20240379548
    Abstract: A semiconductor device includes a patterned wiring layer disposed above a semiconductor substrate, the patterned wiring layer including a plurality of wiring portions, and adjacent wiring portions being separated from each other. The semiconductor device also includes a first insulating passivation layer disposed over the wiring portions in a region between adjacent wiring portions, the first insulating passivation layer having a horizontal surface in the region between adjacent wiring portions. The semiconductor device further includes a second insulating passivation layer disposed on the first insulating passivation layer. The first insulating passivation layer and the second insulating passivation layer do not have a void in the region between adjacent wiring lines.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Wei Cheng, Chyi-Tsong Ni
  • Publication number: 20240371921
    Abstract: A semiconductor device may include one or more low dielectric constant (low-?) layers on a substrate. The semiconductor device may include a dielectric layer on the one or more low-? layers. The semiconductor device may include a structure through the substrate, the one or more low-? layers, and the dielectric layer. The semiconductor device may include a liner layer between the structure and the substrate, between the structure and the one or more low-? layers, and between the structure and the dielectric layer. The semiconductor device may include a capping layer between the liner layer and the dielectric layer and between the liner layer and the one or more low-? layers.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Kuang-Wei CHENG, Chyi-Tsong NI
  • Publication number: 20240363578
    Abstract: A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Kuang-Wei CHENG, Chyi-Tsong NI
  • Patent number: 12131962
    Abstract: A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Wei Cheng, Yung-Tsun Liu, Chih-Tsung Lee, Chyi-Tsong Ni
  • Publication number: 20240347363
    Abstract: The present disclosure relates to systems and methods for reducing the humidity within a FOUP (Front Opening Unified Pod) when loaded on an EFEM (Equipment Front End Module) for transfer of a semiconductor wafer substrate during fabrication processes. A deflector of specified structure is placed inside the EFEM above the load port of the FOUP. The deflector directs airflow in the EFEM away from the load port. The deflector includes a body with a plurality of apertures in the deflector body, and with a sloped front surface. Thus, the degree of penetration of high-humidity air from the EFEM into the FOUP is reduced.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Sung-Ju Huang, Kuang-Wei Cheng, Cheng-Lung Wu, Yi-Fam Shiu, Chyi-Tsong Ni
  • Publication number: 20240339310
    Abstract: An apparatus and method for physical vapor deposition includes a magnetron having a plurality of electromagnets disposed between a base and a magnetic conductive plate. The magnetron includes a plurality of individually controlled electromagnets between a base and an electromagnetic plate. The magnetron controls the polarity and strength of current supplied to the respective electromagnets to generate magnetic fields that confine electrons to areas near a target material within the deposition chamber.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Yu-Young WANG, Wen-Cheng YANG, Chyi-Tsong NI
  • Patent number: 12094849
    Abstract: A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Wei Cheng, Chyi-Tsong Ni
  • Patent number: 12091752
    Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ting Tsai, Chung-Liang Cheng, Wen-Cheng Cheng, Che-Hung Liu, Yu-Cheng Shen, Chyi-Tsong Ni
  • Patent number: 12084769
    Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Tsun Liu, Kuang-Wei Cheng, Sheng-chun Yang, Chih-Tsung Lee, Chyi-Tsong Ni
  • Patent number: 12068363
    Abstract: A semiconductor device may include one or more low dielectric constant (low-?) layers on a substrate. The semiconductor device may include a dielectric layer on the one or more low-? layers. The semiconductor device may include a structure through the substrate, the one or more low-? layers, and the dielectric layer. The semiconductor device may include a liner layer between the structure and the substrate, between the structure and the one or more low-? layers, and between the structure and the dielectric layer. The semiconductor device may include a capping layer between the liner layer and the dielectric layer and between the liner layer and the one or more low-? layers.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Wei Cheng, Chyi-Tsong Ni
  • Patent number: 12068277
    Abstract: A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Wei Cheng, Chyi-Tsong Ni