Patents by Inventor Chyi-Tsong Ni
Chyi-Tsong Ni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9240611Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.Type: GrantFiled: January 15, 2013Date of Patent: January 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Sue
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Publication number: 20160009550Abstract: A method of fabricating a micro electro mechanical system (MEMS) structure includes providing a first substrate structure including a bonding pad structure. The bonding pad structure has at least one recess therein. A second substrate structure is provided and bonded with the bonding pad structure of the first substrate structure.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Ting-Ying Chien, Ching-Hou Su, Chyi-Tsong Ni, Yi Hsun Chiu
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Publication number: 20150340337Abstract: An apparatus includes a bonding system configured to bond at least two wafers. The bonding system has a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers. The apparatus also includes sensors configured to detect data related to a flag-out condition of the flags of the plurality of flag. The apparatus further includes at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Yun-Tai SHIH, Kuan-Ming PAN, Jeng-Hao LIN, I-Shi WANG, Jui-Mu CHO, Ching-Hou SU, Chyi-Tsong NI, Wun-Kai TSAI
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Patent number: 9139423Abstract: A micro electro mechanical system (MEMS) structure includes a first substrate structure including a bonding pad structure. The bonding pad structure has at least one recess therein. A second substrate structure is bonded with the bonding pad structure of the first substrate structure.Type: GrantFiled: January 19, 2012Date of Patent: September 22, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Ying Chien, Yi Hsun Chiu, Ching-Hou Su, Chyi-Tsong Ni
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Patent number: 9123754Abstract: An apparatus is disclosed for detecting flag velocity during a eutectic process for bonding two wafers. The apparatus includes a plurality of sensors for detecting a time and/or velocity of a plurality of flags within a flag-out mechanism. The apparatus also includes one or more displays displaying time durations associated with the movement of the flags during the bonding process. Also disclosed is a method of aligning wafers in a eutectic bonding process. The method includes determining one or more time durations associated with the movement of the flags in the plurality of flags. The method also includes determining if a misalignment has occurred based on the one or more time durations associated with the movement of the flags.Type: GrantFiled: October 6, 2011Date of Patent: September 1, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai Shih, Kuan-Ming Pan, Jeng-Hao Lin, I-Shi Wang, Jui-Mu Cho, Ching-Hou Su, Chyi-Tsong Ni, Wun-Kai Tsai
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Publication number: 20150206917Abstract: Embodiments of an image-sensor device structure and a method of manufacturing thereof are provided. The image-sensor device structure includes a semiconductor substrate and a light-sensing region in the semiconductor substrate. The image-sensor device structure also includes an interconnect structure over the semiconductor substrate, and the interconnect structure includes a transparent dielectric layer over the light-sensing region. The transparent dielectric layer has an optical transmittance ranging from about 90% to about 97%.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ming CHIU, Chun-Yan CHEN, Chyi-Tsong NI, Ruei-Hung JANG
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Publication number: 20150200120Abstract: In accordance with some embodiments, systems and methods for processing a semiconductor substrate are provided. The method includes loading a semiconductor substrate from a chamber to a transfer module, detecting a center and a notch of the semiconductor substrate by the transfer module, and transferring the semiconductor substrate from the transfer module to a process chamber.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Yuan CHEN, Chyi-Tsong NI, Wen-Kung CHENG, Huai-Te HUANG
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Publication number: 20140217557Abstract: A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Ying Chen, Yi Hsun Chiu, Ching-Hou Su, Chyi-Tsong Ni
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Publication number: 20140199597Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Sue
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Patent number: 8741738Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.Type: GrantFiled: June 8, 2011Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi Hsun Chiu, Ting-Ying Chien, Ching-Hou Su, Chyi-Tsong Ni
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Patent number: 8643151Abstract: An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.Type: GrantFiled: February 28, 2011Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Liu, Chyi-Tsong Ni, Hsiao-Yin Lin, Chung-Min Lin
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Publication number: 20130187245Abstract: A micro electro mechanical system (MEMS) structure includes a first substrate structure including a bonding pad structure. The bonding pad structure has at least one recess therein. A second substrate structure is bonded with the bonding pad structure of the first substrate structure.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Ying CHIEN, Yi Hsun CHIU, Ching-Hou SU, Chyi-Tsong NI
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Publication number: 20130130496Abstract: A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.Type: ApplicationFiled: January 16, 2013Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chyi-Tsong NI, I-Shi WANG, Hsin-Kuei LEE, Ching-Hou SU
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Publication number: 20130086786Abstract: An apparatus is disclosed for detecting flag velocity during a eutectic process for bonding two wafers. The apparatus includes a plurality of sensors for detecting a time and/or velocity of a plurality of flags within a flag-out mechanism. The apparatus also includes one or more displays displaying time durations associated with the movement of the flags during the bonding process. Also disclosed is a method of aligning wafers in a eutectic bonding process. The method includes determining one or more time durations associated with the movement of the flags in the plurality of flags. The method also includes determining if a misalignment has occurred based on the one or more time durations associated with the movement of the flags.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai SHIH, Kuan-Ming PAN, Jeng-Hao LIN, I-Shi WANG, Jui-Mu CHO, Ching-Hou SU, Chyi-Tsong NI, Wun-Kai TSAI
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Patent number: 8378490Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.Type: GrantFiled: March 15, 2011Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Tsong Ni, I-Shi Wang, Hsin-Kuei Lee, Ching-Hou Su
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Publication number: 20120313246Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi Hsun CHIU, Ting-Ying CHIEN, Ching-Hou SU, Chyi-Tsong NI
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Publication number: 20120235301Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chyi-Tsong NI, I-Shi WANG, Hsin-Kuei LEE, Ching-Hou SU
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Publication number: 20120217633Abstract: An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Hao LIU, Chyi-Tsong NI, Hsiao-Yin LIN, Chung-Min LIN
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Patent number: 7851358Abstract: A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).Type: GrantFiled: May 5, 2005Date of Patent: December 14, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun Wu, Wen-Long Lee, Chyi-Tsong Ni, Shih-Chi Lin
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Patent number: 7635651Abstract: A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.Type: GrantFiled: August 23, 2005Date of Patent: December 22, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Long Lee, Jun Wu, Shih-Chi Lin, Chyi-Tsong Ni