Abstract: A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

Abstract: A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200 ° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Abstract: A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

Abstract: A method for forming a microelectronic layer while employing a sputtering method employs a reactor chamber. A sputtering target and a substrate are positioned within the reactor chamber, along with a sputtering target heater at a side of sputtering target opposite the substrate. At least one of: (1) a heater to sputtering target distance; (2) sputtering power; (3) deposition time; and (4) sputtering gas flow rate, is controlled in accord with a pre-determined function of sputtering target lifetime to provide enhanced uniformity of the deposited layer.

Abstract: A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.

Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.

Abstract: A method for forming porous silicon oxide film, comprising the following steps. A CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon oxide film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.

Abstract: A new method of creating a relatively thick layer of PE silicon nitride. A conventional method of creating a layer of silicon nitride applies a one-step process for the creation thereof. Film stress increases as the thickness of the created layer of PE silicon nitride increases. A new method is provided for the creation of a crack-resistant layer of PE silicon nitride by providing a multi-step process. The main processing step comprises the creation of a relatively thick, compressive film of PE silicon nitride, over the surface of this relatively thick layer of PE silicon nitride is created a relatively thin (between about 150 and 500 Angstrom) layer of tensile stress PE silicon nitride. This process can be repeated to create a layer of PE silicon nitride of increasing thickness.

Abstract: A process for increasing the surface area of a DRAM capacitor structure via definition of a capacitor in a porous insulator layer, wherein the porous insulator layer is comprised with voids, has been developed. The process features the use of an anisotropic dry etch procedure to form a capacitor opening in a porous insulator layer, exposing a portion of the voids located on the sides of the capacitor opening extending into the porous insulator layer. An isotropic wet etch is then used to enlarge the surface area of the exposed voids, allowing the surface area for a subsequently formed, overlying storage node structure, to be increased.

Abstract: A method of fabricating notching free metal interconnection lines by utilizing aluminum nitride (AlN) as an anti-reflection coating. First, field oxide regions are formed on a semiconductor silicon wafer. Then, electrical element structures such as transistor, capacitor and resistor are formed on the predetermined area. Next, a barrier layer, a metal layer and an anti-reflection layer are successively deposited overlaying the entire silicon wafer surface. Next, the photoresist pattern is formed by the conventional lithography technique. By using photoresist pattern as an etching protection mask, the barrier layer, metal layer and anti-reflection layer are also patterned to form metal interconnection lines. Thereafter, the photoresist is stripped by oxygen plasma and sulfuric acid.

Abstract: The present invention discloses a method for reducing the reflectivity of a silicide layer. This invention utilizes a rapid thermal oxidation process to treat a tungsten silicide film in order to reduce the reflectivity of the tungsten silicide film. Thus, an anti-reflectivity layer is not required in the present invention. In addition simplify the present invention, a thin oxide layer is growth on the tungsten suicide layer during the rapid thermal oxidation process and the thin oxide layer serves as a hard mask in subsequent steps. In addition, because utilizing the rapid thermal process, the present invention can greatly reduce the resistance of the tungsten silicide in order to increase the speed of the devices.