Patents by Inventor Claire Fenouillet-Beranger

Claire Fenouillet-Beranger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028728
    Abstract: The invention relates to a method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, said device comprising active components (23) formed in active areas of the substrate (10) separated by isolation trenches and which are delimited by first sidewalls (19B), said isolation trenches being filled, at least partially, with a first dielectric material, the method comprising: a step of chemically attacking a passive section (21) of the first bottom of the isolation trenches intended to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm, a step of forming a passive component (27), covering the first dielectric material and directly above the passive section (21).
    Type: Application
    Filed: July 21, 2021
    Publication date: January 27, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Heimanu NIEBOJEWSKI, François ANDRIEU, Claire FENOUILLET-BERANGER
  • Patent number: 10930562
    Abstract: A connection structure for microelectronic device with superposed semi-conductor layers including a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, the connection structure further including a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Fabrice Nemouchi, Maud Vinet
  • Publication number: 20190371671
    Abstract: Connection structure for microelectronic device with superposed semi-conductor layers comprising a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, said connection structure further comprising a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: December 5, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire FENOUILLET-BERANGER, Fabrice NEMOUCHI, Maud VINET
  • Patent number: 10319628
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 11, 2019
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien Deprat, Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Maud Vinet
  • Patent number: 10199276
    Abstract: Fabrication of an integrated circuit comprising: at least one first transistor made at least partially in a first semiconducting layer, at least one second transistor made at least partially in a second semiconducting layer formed above the first semiconducting layer, an insulating layer formed between the first transistor and the second transistor, one or several connection elements passing through the insulating layer between the first and the second transistor, at least one connection element being connected to the first and/or the second transistor and being based on a metal-semiconductor alloy.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 5, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Fabrice Nemouchi
  • Patent number: 10121707
    Abstract: A method for making a FET transistor, including the following steps: making, on a crystalline semiconducting layer, a layer of gate dielectric on which a gate conducting layer is arranged, etching the conducting layer such that a remaining portion of this layer fully covers a first semiconducting portion forming an active zone and a second semiconducting portion adjacent to the active zone, implanting atoms and/or dopants in the semiconducting layer, thus amorphizing the semiconductor around the first portion and that of the second portion, etching the remaining portion of the conducting layer and of the dielectric layer according to a gate pattern partially covering the first portion and the second portion, forming the gate and a gate overflow, etching the amorphous semiconductor.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 6, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Philippe Coronel
  • Patent number: 10115637
    Abstract: Method for fabricating transistors for an integrated 3D circuit, comprising: a) forming, on a given level of transistors made in a first semiconductor layer: a stack comprising a first region of a second semiconductor zone suitable for an N-type transistor channel and a second region of the second semiconductor zone suitable for a P-type transistor channel of a higher level, the stack moreover comprising a ground plane continuous layer (40), as well as an insulating layer between the ground plane and the second semiconductor layer, then b) exposing source and drain zones of the circuit to a laser (L), so as to carry out at least one thermal activation annealing, where the exposed source and drain zones are located next to an upper surface of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect at least a part of the circuit located on the side of a lower face of the ground plane continuous layer from the laser, then c) carrying out cutting up of the grou
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 30, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Benoit Mathieu, Philippe Coronel
  • Patent number: 10074802
    Abstract: Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 11, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Elisa Vianello
  • Patent number: 10062681
    Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 28, 2018
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National de la Recherche Scientifique
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9997395
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b) providing a second structure successively including a substrate, an active layer, an intermediate layer, a first semiconducting layer and a porous second semiconducting layer; c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer; d) removing the substrate of the second structure so as to expose the active layer; e) adding dopants to the first semiconducting layer or to the active layer; f) irradiating the first semiconducting layer by a pulse laser so as to thermally activate the corresponding dopants.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 12, 2018
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Frédéric-Xavier Gaillard, Benoit Mathieu, Fabrice Nemouchi
  • Publication number: 20180158736
    Abstract: Method for fabricating transistors for an integrated 3D circuit, comprising: a) forming, on a given level of transistors made in a first semiconductor layer: a stack comprising a first region of a second semiconductor zone suitable for an N-type transistor channel and a second region of the second semiconductor zone suitable for a P-type transistor channel of a higher level, the stack moreover comprising a ground plane continuous layer (40), as well as an insulating layer between the ground plane and the second semiconductor layer, then b) exposing source and drain zones of the circuit to a laser (L), so as to carry out at least one thermal activation annealing, where the exposed source and drain zones are located next to an upper surface of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect at least a part of the circuit located on the side of a lower face of the ground plane continuous layer from the laser, then c) carrying out cutting up of the grou
    Type: Application
    Filed: November 22, 2017
    Publication date: June 7, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire FENOUILLET-BERANGER, Benoit MATHIEU, Philippe CORONEL
  • Publication number: 20180144992
    Abstract: A method for making a FET transistor, including the following steps: making, on a crystalline semiconducting layer, a layer of gate dielectric on which a gate conducting layer is arranged, etching the conducting layer such that a remaining portion of this layer fully covers a first semiconducting portion forming an active zone and a second semiconducting portion adjacent to the active zone, implanting atoms and/or dopants in the semiconducting layer, thus amorphising the semiconductor around the first portion and that of the second portion, etching the remaining portion of the conducting layer and of the dielectric layer according to a gate pattern partially covering the first portion and the second portion, forming the gate and a gate overflow, etching the amorphous semiconductor.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire FENOUILLET-BERANGER, Philippe Coronel
  • Publication number: 20180090366
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien DEPRAT, Perrine BATUDE, Laurent BRUNET, Claire FENOUILLET-BERANGER, Maud VINET
  • Patent number: 9852950
    Abstract: Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor a second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 26, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Philippe Coronel
  • Publication number: 20170352583
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b) providing a second structure successively including a substrate, an active layer, an intermediate layer, a first semiconducting layer and a porous second semiconducting layer; c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer; d) removing the substrate of the second structure so as to expose the active layer; e) adding dopants to the first semiconducting layer or to the active layer; f) irradiating the first semiconducting layer by a pulse laser so as to thermally activate the corresponding dopants.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 7, 2017
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire FENOUILLET-BERANGER, Frédéric-Xavier GAILLARD, Benoit MATHIEU, Fabrice NEMOUCHI
  • Patent number: 9793162
    Abstract: Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 17, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Claire Fenouillet-Beranger, Philippe Coronel
  • Patent number: 9786658
    Abstract: This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer; a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device; b) bombarding the polycrystalline semiconductor layer by a beam of species configured to form an amorphous part and to preserve a superficial polycrystalline part; c) bonding the first and second structures; d) removing the second substrate of the second structure; e) introducing dopants into the amorphous part, through the exposed active layer; f) thermally activating the dopants by recrystallization of the amorphous part.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 10, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit Mathieu, Claire Fenouillet-Beranger
  • Patent number: 9779982
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Frank Fournel
  • Patent number: 9761583
    Abstract: A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 12, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Bernard Previtali, Olivier Rozeau
  • Publication number: 20170256531
    Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
    Type: Application
    Filed: May 10, 2017
    Publication date: September 7, 2017
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau