Abstract: A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.

Abstract: Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.

Abstract: The present invention is an apparatus and method for increasing the amount of data on a transmission path on a printed circuit board. Conventional methods allow only one data signal to be transmitted on the transmission path. The present invention uses multiple transmitters to modulate multiple data signals to form multiple modulated signals. The modulated signals are transmitted, possibly simultaneously, on the transmission path to receivers configured to demodulate individual modulated signals and recover the original data signals.

Abstract: An input/output interface is used to transmit data between a transmitting circuit and a receiving circuit. Selectively during both system startup and system operation, a known bit pattern transmitted by the transmitting circuit is compared to a received bit pattern. The received bit pattern may be seen at the receiving circuit or a voltage regulator that is used to control the power supply level of the input/output interface. Dependent on the comparison of the known bit pattern and the received bit pattern, a bit error rate across the input/output interface is determined, in response to which the voltage regulator adjusts the power supply level of the input/output interface.

Abstract: A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.

Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

Abstract: An analog debugging block of an integrated circuit includes a multiplexor, a buffer, and a voltage-controlled oscillator. An analog voltage signal-of-interest is selectively passed through the multiplexor to the buffer. The buffer outputs an analog control voltage dependent on the selected analog voltage signal-of-interest. The analog control voltage serves as an input to the voltage-controlled oscillator and is used to control a frequency of a digital output signal generated from the voltage-controlled oscillator. The digital output signal from the voltage-controlled oscillator is driven off-chip, whereupon a frequency of the digital output signal is determined and compared against a collection of known frequencies that correspond to particular known voltages of the analog voltage signal-of-interest, thereby resulting in a determination of the value of the selected analog voltage signal-of-interest.

Abstract: A method and apparatus for adjusting a frequency characteristic of a signal is provided. A transmitter circuit uses a driver circuit and a filter to generate the signal. The frequency characteristic of the signal is adjusted, or “equalized,” using a replica driver that adjusts the driver circuit and a voltage control circuit that adjusts the filter.

Abstract: A communication system comprising transmitting circuitry arranged to transmit a data signal and a timing signal; and receiving circuitry arranged to receive the data signal and the timing signal. The receiving circuitry comprises a first finite impulse response filter arranged to generate a filtered timing signal dependent on the timing signal and a at least one mixer signal; a decision feedback circuit arranged to generate the at least one mixer signal dependent on the filtered timing signal and a calibration signal; and a second finite impulse response filter arranged to generate a filtered data signal dependent on the data signal and the at least one mixer signal.

Abstract: A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: A plurality of on-chip temperature sensors are selectively distributed across an integrated circuit. The temperature sensors generate signals indicative of operating temperatures experienced by the portions of the integrated circuit on which the temperature sensors are disposed. Based on the temperatures of the portions of the integrated circuit, operation of particular circuitry of the integrated circuit is dynamically adjusted to counteract the effects of undesirable or unexpected operating temperatures.

Abstract: A method and apparatus for enlarging data eyes in a wireline communication system involves pre-coding a data signal before transmission to generate a constant frequency characteristic independent of a state of the pre-coded data signal. The receiving circuit includes a circuit that temporally expands at least a portion of the pre-coded data signal. The portion of the temporally expanded data signal is latched by the receiving circuit.

Abstract: A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.

Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

Abstract: An apparatus for canceling an effect of power supply resonance is provided. The effect of power supply resonance is a variation in power supply voltage potential. This variation may substantially affect an output buffer by causing the output buffer's output to sag below desired values. A voltage regulating circuit is coupled to power supply lines local to the output buffer where the voltage regulating circuit is most effective in reducing voltage potential variation. An exemplary voltage regulating circuit is provided that uses charge-pumped capacitors to raise the power supply voltage potential when it falls below a desired value. A second example of a voltage regulating circuit uses charge-pumped capacitors to lower the power supply voltage potential when it rises above a desired value.

Abstract: A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.

Abstract: A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.

Abstract: An electrolytic cell which comprises at least one anode and at least one cathode, an inlet channel through which liquor may be charged to the electrolytic cell, and an outlet channel through which liquor may be removed from the electrolytic cell, in which the outlet channel is operatively connected to the inlet channel, and in which the inlet channel comprises an ejector. The inlet and outlet channels may be formed in a unit made up of a plurality of shaped sheets, e.g. of electrically non-conducting plastics material, which together form the inlet and outlet channels.