Abstract: A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is arranged to carry a clock signal. The delay locked loop operatively connects to the clock path where the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop. An analog state storage apparatus operatively connects to the delay locked loop and is arranged to store the voltage potential. Also, the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal.

Abstract: An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.

Abstract: A method and apparatus for monitoring a temperature on an integrated circuit that includes a thin gate oxide transistor. A temperature monitoring system that includes a thick gate oxide transistor is provided. The temperature monitoring system includes a temperature independent voltage generator, a temperature dependent voltage generator that includes a thick gate oxide transistor, and a quantifier operatively connected to the temperature independent voltage generator and temperature dependent voltage generator.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: A charge pump is arranged to generate a current dependent on a phase difference between a first signal and a second signal. A reference circuit is operatively connected to the charge pump and arranged to adjust the charge pump so that the charge pump is independent of an aging effect.

Abstract: A SSTL interface voltage translator that uses dynamic biasing to translate an input signal to an output signal is provided. The voltage translator uses a first device that, dependent on a first bias signal, causes the output signal to be pulled down, where the first bias signal is dependent on the input signal. The voltage translator also uses a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.

Abstract: A system and method of determining an in-situ signal path delay on an integrated circuit. The system and method includes inputting a first signal to a first input node of a first signal path and inputting a second signal to a second input node of a reference signal path. A phase of the first signal output from a first output node of the first signal path is compared to a phase of the second signal output from a second output node of the reference signal path. A phase error signal is output.

Abstract: An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.

Abstract: A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.

Abstract: A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

Abstract: A method and apparatus for adjusting clock skew involves sensing a temperature at a location on a microprocessor. A temperature sensor indicates a temperature value of the location on the microprocessor. The temperature value is monitored, and a tunable buffer is adjusted dependent on the monitoring. The tunable buffer is used to adjust clock skew. A memory is arranged to store an adjustment value for the tunable buffer.

Abstract: A method and apparatus for adjusting clock skew involves sensing a temperature at a location on an integrated circuit. A temperature sensor indicates a temperature value of the location on the integrated circuit. The temperature value is monitored, and a tunable buffer is adjusted dependent on the monitoring. The tunable buffer is used to adjust clock skew.

Abstract: A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

Abstract: A method and apparatus adjusts a propagation delay through a receiver circuit. A transmission apparatus is arranged to generate a control signal where an impedance of a driver circuit is dependent on the control signal. A bias generator is operatively connected to the transmission apparatus and is dependent on the control signal. A receiver circuit is operatively connected to the bias generator where the bias generator is arranged to operatively adjust a propagation delay through the receiver circuit.

Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.

Abstract: A delay locked loop design uses a fixed capacitance to load down a signal output from a phase selector of the delay locked loop to a phase interpolator of the delay locked loop. Such loading counteracts for variable capacitive coupling that occurs in the phase interpolator as interpolation weights to the phase interpolator change. Without such loading of the output of the phase selector, the delay of the phase selector varies as a function of the capacitance coupling of the phase interpolator.

Abstract: A flip-flop with built-in voltage translation is used in a transmission system so as to combine core flip-flop circuitry with a input/output voltage translator. The flip-flop with built-in voltage translation dynamically latches data and translates a core power supply voltage swing at an input of the flip-flop to an input/output power supply voltage swing at an output of the flip-flop. Thus, the flip-flop, dependent on a clock input, is able to output a data signal having a translated voltage swing.

Abstract: The present invention is an apparatus and method for increasing the amount of data on a transmission path on a printed circuit board. Conventional methods allow only one data signal to be transmitted on the transmission path. The present invention uses multiple transmitters to modulate multiple data signals to form multiple modulated signals. The modulated signals are transmitted, possibly simultaneously, on the transmission path to receivers configured to demodulate individual modulated signals and recover the original data signals.

Abstract: A computer system uses a power distribution network arranged to propagate at least one voltage potential to an integrated circuit. A resonance detector is arranged to detect a power supply resonance. A damping circuit is operatively connected to the resonance detector and the power distribution network. The damping circuit resides external to the integrated circuit and dampens the power supply resonance under control of the resonance detector.

Abstract: A pulse driver circuit for data transmission uses multiple delay and driver stages to shape an input data pulse into a Nyquist-like data pulse. The delay stages each input the input data pulse, and then, dependent on the state of particular delay stages, output portions of the input data pulse, which are then driven by the driver stages so as to generate a data pulse having a shorter temporal width than the corresponding input data pulse.