Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

Abstract: A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: An on-chip voltage sensor that selectively eliminates noise from a voltage measurement is provided. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of a computer chip to be measured exclusive of high-frequency noise. Further, a method for measuring a voltage on a section of a computer chip using a voltage divider having a resistor and a capacitor is provided. Further, a computer chip having an on-chip voltage sensor is provided. Further, a method and apparatus for observing voltages at multiple locations on an integrated circuit.

Abstract: An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.

Abstract: A method and apparatus for post-fabrication calibration and adjustment of a delay locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the leakage current may be stored and subsequently read to adjust the delay locked loop.

Abstract: A controller and method are provided for monitoring and controlling a temperature of an integrated circuit to inhibit damage from a thermal problem. The controller and method allow for individual temperature thresholds for each of one or more temperature sensors. Digital filtering of values received from temperature sensors is also provided. A variety of actions can be selected for execution upon a determination of an over-temperature condition of the integrated circuit, including assert an over-temperature pin, assert an over-temperature bit in an error register of said controller, assert an over-temperature bit in an error register of said microprocessor, issue an over-temperature interrupt to a service bus of said integrated circuit, cause a trap, slow an operating frequency of said integrated circuit, stop said integrated circuit, and do nothing.

Abstract: An apparatus and method are provided for sensing a physical stimulus of an integrated circuit. The apparatus and method allow for accurate die temperature measurements of the integrated circuit and are able to provide a highly accurate die temperature measurement without the need for an independent voltage source or current source.

Abstract: A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

Abstract: A delay locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the delay locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the delay locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.

Abstract: A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.

Abstract: A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.

Abstract: A phase locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the phase locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the phase locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract: A method and apparatus for post-fabrication adjustment of a phase locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the phase locked loop. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated.

Abstract: A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.

Abstract: A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.

Abstract: A method for reducing noise in an I/O system has been developed. The method includes powering up the I/O supply and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the I/O power supply, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A circuit for reducing the noise associated with a clock signal for a latch based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a predetermined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Abstract: A method for reducing global clock skew by referencing a first point on an integrated circuit to which to align other points on the integrated circuit is provided. Further, an integrated circuit that has localized DLLs having adjustable buffers that selectively drive a signal on a clock grid is provided. Further, a technique for using a local DLL, one or more phase detectors, and one or more DLLs connected to portions of a clock grid to reduce clock skew is provided.

Abstract: A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.