Patents by Inventor Cyrille Dray
Cyrille Dray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11024356Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: September 9, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Publication number: 20200020378Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: ApplicationFiled: September 9, 2019Publication date: January 16, 2020Applicant: Intel CorporationInventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
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Patent number: 10438640Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: August 1, 2018Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Publication number: 20180342277Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: ApplicationFiled: August 1, 2018Publication date: November 29, 2018Applicant: Intel CorporationInventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
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Patent number: 10127959Abstract: Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.Type: GrantFiled: February 27, 2017Date of Patent: November 13, 2018Assignee: Intel IP CorporationInventors: Cyrille Dray, El Mehdi Boujamaa
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Patent number: 10068628Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: June 28, 2013Date of Patent: September 4, 2018Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Patent number: 9875783Abstract: Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide thicknesses.Type: GrantFiled: March 3, 2014Date of Patent: January 23, 2018Assignee: INTEL CORPORATIONInventors: Cyrille Dray, Liqiong Wei
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Patent number: 9865322Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: GrantFiled: September 29, 2016Date of Patent: January 9, 2018Assignee: INTEL CORPORATIONInventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
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Publication number: 20170169874Abstract: Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide thicknesses.Type: ApplicationFiled: March 3, 2014Publication date: June 15, 2017Inventors: Cyrille DRAY, Liqiong WEI
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Publication number: 20170169870Abstract: Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: Cyrille Dray, El Mehdi Boujamaa
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Publication number: 20170092337Abstract: Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: Cyrille Dray, El Mehdi Boujamaa
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Patent number: 9601165Abstract: Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.Type: GrantFiled: September 24, 2015Date of Patent: March 21, 2017Assignee: Intel IP CorporationInventors: Cyrille Dray, El Mehdi Boujamaa
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Publication number: 20170018298Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
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Patent number: 9478273Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: GrantFiled: October 31, 2013Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
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Patent number: 9418761Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.Type: GrantFiled: December 12, 2014Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Umut Arslan, Cyrille Dray
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Publication number: 20160172059Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: Umut Arslan, Cyrille Dray
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Publication number: 20160125927Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: ApplicationFiled: June 28, 2013Publication date: May 5, 2016Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
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Patent number: 9286976Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.Type: GrantFiled: May 29, 2014Date of Patent: March 15, 2016Assignee: INTEL CORPORATIONInventors: Blake Lin, Cyrille Dray, Ananda Roy, Liqiong Wei, Fatih Hamzaoglu
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Patent number: 9263121Abstract: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.Type: GrantFiled: May 16, 2013Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Eric A. Karl, Yong-Gee Ng, Cyrille Dray
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Patent number: 9230636Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.Type: GrantFiled: December 20, 2013Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Pascal A. Meinerzhagen, Jaydeep P. Kulkarni, Muhammad M. Khellah, Cyrille Dray, Dinesh Somasekhar, James W. Tschanz, Vivek K. De