Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.

Abstract: A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase.

Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

Abstract: A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase.

Abstract: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.

Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.

Abstract: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.

Abstract: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.

Abstract: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.

Abstract: The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed.

Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

Abstract: An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a 0-ranking potential is applied, and the output. The device according to the invention also comprises: a means to produce n?1 potentials ranked 1 to n?1 included between the potential ranked 0 and the potential ranked n; and a driving means for the production, from the n+1 potentials ranked 0 to n, of control signals suited to driving the gates of the transistors of the first arm and the gates of the transistors of the second arm so that the transistors of one of the arms are on and the transistors of the other arm are off depending on the value of the n-ranking potential relative to the value of the 0-ranking potential.