Abstract: An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed.

Abstract: The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level.

Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.

Abstract: The invention relates to a device, and also to a corresponding method of implementation, for SRAM memory information storage, powered by a voltage VDD and comprising: an array of base cells organised in base columns, and at least one mirror column of mirror cells, liable to simulate the behaviour of the cells in a base column, The invention is characterised in that the device further comprises: Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying the mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD<i>) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.

Abstract: An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a 0-ranking potential is applied, and the output. The device according to the invention also comprises: a means to produce n?1 potentials ranked 1 to n?1 included between the potential ranked 0 and the potential ranked n; and a driving means for the production, from the n+1 potentials ranked 0 to n, of control signals suited to driving the gates of the transistors of the first arm and the gates of the transistors of the second arm so that the transistors of one of the arms are on and the transistors of the other arm are off depending on the value of the n-ranking potential relative to the value of the 0-ranking potential.

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.

Abstract: A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD<i>) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.

Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Abstract: A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a control grid, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of grid material EG, FL P2 in which the floating grid FG is made extends integrall above the active area ZA without overlapping part of the isolation region STI, and the transistor is electrically isolated from the control grid CG by PN junctions that will be reverse biased.

Abstract: A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Abstract: Control device for a generation circuit (REF) for reference voltages (VPOL1, VPOL2), includes a first P type MOS transistor (M12), connected between a node (N) to which a high voltage signal (EHV) is applied and a first intermediate node (A), a second P type MOS transistor (M13) connected between the first intermediate node (A) and a second intermediate node (B), and a third P type MOS transistor (M14) connected between the second node and the ground and with its grid connected to its drain, to supply a reference voltage (VPOL1, VPOL2) on one of the first and second intermediate nodes (A, B). The control device includes a controlling mechanism for controlling the reference transistors, either in a first or second operating mode.