Abstract: A metal-containing photoresist film may be deposited on a semiconductor substrate using a dry deposition technique. Unintended metal-containing photoresist material may form on internal surfaces of a process chamber during deposition, bevel and backside cleaning, baking, development, or etch operations. An in situ dry chamber clean may be performed to remove the unintended metal-containing photoresist material by exposure to an etch gas. The dry chamber clean may be performed at elevated temperatures without striking a plasma. In some embodiments, the dry chamber clean may include pumping/purging and conditioning operations.

Abstract: The present disclosure provides a semiconductor device and an operating method thereof, and a system. The semiconductor device includes a memory cell array, word lines coupled to the memory cell array, and a peripheral circuit coupled to the word lines, wherein the peripheral circuit is configured to: perform a first program operation on a target memory cell set of a plurality of memory cell sets coupled to a selected word line, wherein the first program operation includes a plurality of first program cycles; and the target memory cell set includes a plurality of memory cells whose threshold voltages are to be programmed into a target threshold voltage distribution; and perform a second program operation on the target memory cell set, wherein the second program operation includes at least one second program cycle, the second program cycle includes a verify phase and a program phase after the verify phase.

Abstract: An example method of operating a memory device includes performing a program operation on a first memory cell in a first program operation phase and performing a program operation on a second memory cell and applying a program-inhibiting voltage to a first bit line coupled to the first memory cell in a second program operation phase. The first memory cell and the second memory cell are coupled to a same word line. A target threshold voltage of the first memory cell is greater than a target threshold voltage of the second memory cell. The first program operation phase precedes the second program operation phase.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a peripheral circuit. The semiconductor device may include a memory cell array. The peripheral circuit may be coupled to the memory cell array, the memory cell array may include a plurality of memory regions, and each memory region may include a first number of memory blocks. The peripheral circuit may be configured to receive an operation instruction. The operation instruction may include address information for determining a target memory region in the plurality of memory regions and a second number of working memory blocks in the target memory region. The second number may be less than the first number. The peripheral circuit may be configured to perform a corresponding operation on the working memory blocks in response to the operation instruction.

Abstract: A battery pack includes multiple cells; a cell bracket configured to support the multiple cells; and a terminal assembly electrically connected to the multiple cells and configured to be coupled to an interface of a power tool. The cell bracket is at least partially exposed to an external environment, and the thermal conductivity of the cell bracket is higher than or equal to 0.5 W/(m·K). The temperature of the battery pack can be accurately detected, the cycling efficiency of the battery pack is ensured, and the risk of explosion caused by thermal runaway of the battery can be eliminated.

Abstract: A motor vehicle includes a heat pump with an expansion valve and a controller that is configured to control a position of the expansion valve based, at least in part, on a superheat target, and utilize differences between an expected position of the expansion valve and a controlled position of the expansion valve to estimate a refrigerant level of the heat pump and/or a remaining useful life of the heat pump. The controller is optionally configured to determine a plurality of estimated refrigerant levels during closed loop control of the heat pump system and utilize the plurality of estimated refrigerant levels to determine a trend in refrigerant level over time.

Abstract: A disclosed semiconductor device comprises a first semiconductor structure comprising an analog-to-digital converter circuit and a data processing circuit; and a second semiconductor structure comprising a memory array and a peripheral circuit coupled to the memory array; wherein the analog-to-digital converter circuit is coupled with the memory array and configured to convert analog computation information based on a first operation performed by the memory array into digital information, and the data processing circuit is coupled with the analog-to-digital converter circuit and configured to perform a second operation based on the digital information.

Abstract: The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.

Abstract: Process condition management facilitates the combination of dry development and post-development treatment into a single process chamber, eliminating the necessity for a post-dry development bake step in a separate chamber during semiconductor manufacturing. Thermal dry development and plasma dry development may be performed in the same chamber. Thermal dry development, plasma dry development and passivation such as an O2 flash treatment; or thermal dry development, plasma dry development, passivation and hardening operations are enabled without wafer transfer.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, applying, to a second word line, a first pass voltage during a first stage and a second pass voltage during a second stage; during a second loop, applying a second program voltage to the first word line, applying, to the second word line, a third pass voltage during a first stage and a fourth pass voltage during a second stage; and during a third loop, applying a third program voltage to the first word line, applying, to the second word line, a fifth pass voltage during a first stage and a sixth pass voltage during a second stage. The third pass voltage is lower than the first pass voltage and the fifth pass voltage.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a memory array comprising a first memory string and a second memory string. The first memory string may include at least one first dummy memory cell. The semiconductor device may include a peripheral circuit coupled to the memory array and configured to perform a program operation on the at least one first dummy memory cell, such that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold. In a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, a difference between a current of the first memory string and a current of the second memory string may be less than or equal to a preset threshold.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, and applying, to a second word line, a first pass voltage during a first stage of the first loop and a second pass voltage during a second stage of the first loop. The method further includes, during a second loop of the program operation, applying a second program voltage to the first word line, and applying, to the second word line, a third pass voltage during a first stage of the second loop and a fourth pass voltage during a second stage of the second loop. A difference between the fourth pass voltage and the third pass voltage is greater than a difference between the second pass voltage and the first pass voltage.

Abstract: Examples of present disclosure disclose a memory device and an operation method thereof, and a readable storage medium. The memory device includes: a first memory region and a second memory region, each including a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region and configured to: when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually; and when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually.

Abstract: Techniques described herein relate to methods, apparatus, and systems for promoting adhesion between a substrate and a metal-containing photoresist. For instance, the method may include receiving the substrate in a reaction chamber, the substrate having a first material exposed on its surface, the first material including a silicon-based material and/or a carbon-based material; generating a plasma from a plasma generation gas source that is substantially free of silicon, where the plasma includes chemical functional groups; exposing the substrate to the plasma to modify the surface of the substrate by forming bonds between the first material and chemical functional groups from the plasma; and depositing the metal-containing photoresist on the modified surface of the substrate, where the bonds between the first material and the chemical functional groups promote adhesion between the substrate and the metal-containing photoresist.

Abstract: A method of performing 3D metrology on a structure includes directing an electron beam onto a surface of the structure, capturing a first set of images of the structure at a first landing angle, capturing a second set of images of the structure at a second landing angle, the second landing angle being different from the first landing angle, and determining, by comparing the first set of images to the second set of images, at least one 3D parameter of the structure. The first set of images at the first landing angle and the second set of images at the second landing angle are captured in a single run of the electron beam across the surface of the structure.

Abstract: A method of calibrating a landing angle of an electron beam includes fabricating a landing angle standard structure, determining a tilt angle of the landing angle standard structure relative a reference plane, scanning the landing angle standard structure to generate a plurality of images of the landing angle standard structure, determining a width difference between a first sidewall formed on the landing angle standard structure and a second sidewall formed on the landing structure, determining, using the width difference between the first sidewall and the second sidewall, a beam tilt of the electron beam, determining, by comparing the beam tilt of the electron beam to the tilt angle of the landing angle standard structure, the landing angle of the electron beam, and adjusting the electron beam, such that the landing angle of the electron beam is normal to a surface of the landing angle standard structure.

Abstract: The present disclosure provides a chip, a microfluidic device. The chip includes a first container for accommodating a first fluid, a second container for accommodating a second fluid, a delivery channel including a first flow channel communicating with the first container and a second flow channel communicating with the second container, the first flow channel and the second flow channel intersecting and communicating with each other at a junction, and at least one collector. The delivery channel allows the first and second fluids to meet at the junction to generate droplets. The first flow channel comprises a first, a second and a third sub-portions, the second flow channel comprises a first, a second and a third portions. An area of a first cross-section of the second sub-portion at the junction is greater than or equal to an area of a second cross-section of the second portion at the junction.

Abstract: Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using a halide-containing chemistry such as a hydrogen halide. A metal-containing resist film may be deposited on a semiconductor substrate using a dry or wet deposition technique. The resist film may be an EUV-sensitive organo-metal oxide or organo-metal-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using wet or dry development.

Abstract: Provided are processes for development of photopatterned metal or metal oxide-based thin film photoresists post-EUV exposure for removal of non-volatile species and deterring etch stop. Repeated cycles of alternating treatment with an etchant and an oxidizing agent; or treatment with an etchant followed by treatment with a wash agent are effective techniques for removal of the undesired unexposed portion of a photoresist.

Abstract: Provided herein are nanobodies, polypeptides comprising the same, and uses thereof. The nanobody's variable region includes 3 complementarity determining regions (CDRs) and framework regions (FRs), wherein the CDRs are as follows: CDR1: Ser-Gly-Xaa11-Xaa12-Phe-Xaa13-Xaa14-Asn-Xaa15 (Formula I); CDR2: Xaa21-Thr-Xaa22-Xaa23-Gly-Xaa24-Thr (Formula II); CDR3: His-Xaa31-Asp-Glu-Xaa32-Arg-Xaa33-Ser-Xaa34-Trp-Thr-Thr-Ser-Asn-Xaa35 (Formula III). The nanobodies and their polypeptides exhibit high affinity and activity, specifically recognizing and binding AAV. Affinity agents prepared therefrom have strong AAV adsorption capacity, suitable for AAV affinity chromatography to facilitate its industrial application. They are also applicable to AAV detection, enabling simultaneous detection of empty capsids and viral particles.