Abstract: An example memory device includes: a memory cell array, a plurality of word lines, and a peripheral circuit configured to: apply a first verification voltage to a selected word line, where a plurality of memory cells connected to the selected word line includes a first group of memory cells and a second group of memory cells, threshold voltages for first memory cells in the first group of memory cells are smaller than the first verification voltage, and threshold voltages for second memory cells in the second group of memory cells are greater than or equal to the first verification voltage; and perform a program operation on at least a portion of the first memory cells in the first group of memory cells and the second memory cells in the second group of memory cells. Threshold voltages corresponding to the target memory states are smaller than the first verification voltage.

Abstract: Systems, devices, and methods for manufacturing and operating a ferroelectric memory device are provided. In one aspect, a method of operating a ferroelectric memory device includes: performing a program operation on a first ferroelectric memory cell, including: applying a program voltage to a first word line coupled to the first ferroelectric memory cell; applying a pass voltage to a second word line coupled to a second ferroelectric memory cell; applying a first voltage to a selected top select gate (TSG); and applying a second voltage greater than the first voltage to an unselected TSG.

Abstract: Systems, devices, and methods for manufacturing and operating a ferroelectric memory device are provided. In one aspect, a semiconductor device includes a ferroelectric memory cell, including: a first conductive layer; a dielectric layer in contact with the first conductive layer; a channel layer in contact with the dielectric layer; a ferroelectric layer in contact with the channel layer; and a second conductive layer in contact with the ferroelectric layer, where the channel layer is between the first conductive layer and the second conductive layer, and the ferroelectric layer is between the channel layer and the second conductive layer.

Abstract: The present disclosure relates to stacks having a sensitized resist film, as well as methods and apparatuses for applying such sensitized films. In particular embodiments, the sensitizer can be provided in gas form, and unreacted sensitizer precursors can be recovered after a deposition step.

Abstract: A metal-containing photoresist film may be deposited on a semiconductor substrate using a dry deposition technique. Unintended metal-containing photoresist material may form on internal surfaces of a process chamber during deposition, bevel and backside cleaning, baking, development, or etch operations. An in situ dry chamber clean may be performed to remove the unintended metal-containing photoresist material by exposure to an etch gas. The dry chamber clean may be performed at elevated temperatures without striking a plasma. In some embodiments, the dry chamber clean may include pumping/purging and conditioning operations.

Abstract: Systems, devices, and methods for operating a ferroelectric device are provided. In one aspect, a method of operating a ferroelectric memory device includes: performing, during a first phase, a program operation on a first ferroelectric memory cell, including: applying a program voltage to a first word line coupled to the first ferroelectric memory cell, and applying a pass voltage to a second word line coupled to a second ferroelectric memory cell; and performing, during a second phase after the first phase, a second operation, including: applying a first voltage to the second word line; applying a second voltage to a source line; and applying a third voltage to a bit line. At least one of the second voltage or the third voltage is greater than the first voltage.

Abstract: A method includes discharging a voltage of a first word line to a first voltage after performing a first read operation on a first memory cell; floating the first word line after discharging the voltage of the first word line to the first voltage; applying a second voltage to the first word line in a first phase of performing a second read operation on the first memory cell, wherein the second read operation is after floating the first word line, and the second voltage is greater than the first voltage; and applying a pre pulse voltage to the first word line in a second phase of performing the second read operation, wherein the second phase is after the first phase, and the pre pulse voltage is greater than the second voltage.

Abstract: Methods, devices, and systems for managing program operations are provided. In one aspect, a memory system includes a memory device, and a memory controller coupled to the memory device. The memory controller is configured to instruct the memory device to write first data in a first single-level cell (SLC) mode using a first program pulse, and in response to detecting that the memory system is disconnected from an external power source, instruct the memory device to write second data in a second SLC mode using a second program pulse. The second program pulse is different from the first program pulse.

Abstract: The present disclosure provides a semiconductor device including a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory banks, and each of the memory banks includes at least one memory block in a first type of program state; the peripheral circuit writes data of at least one first memory block into at least one second memory block to obtain the second memory block in a second type of program state. The first memory block and the second memory block are different memory blocks in memory blocks of a target memory bank, and the first memory block includes a memory block in the first type of program state; and erase data of the first memory block, until each memory block in the first type of program state in the target memory bank is erased once.

Abstract: The examples of the present disclosure provide a memory device, an operating method thereof, and a memory system. The memory device includes: a memory cell array; word lines coupled to the memory cell array; a peripheral circuit coupled to the memory cell array and the word lines, wherein the peripheral circuit is configured to: in a first programming operation, apply a first pass voltage to a first group of word lines during a first time period; apply a second pass voltage greater than the first pass voltage to the first group of word lines during a second time period after the first time period; and apply a third pass voltage to a second group of word lines during a third time period.

Abstract: In some examples, a peripheral circuit is configured to: when performing a first read operation on memory cells coupled to a selected word line, apply a first pass voltage to a first word line, apply a second pass voltage to a second word line, and apply a third pass voltage to a third word line, wherein the first word line comprises at least one word line physically located above and below the selected word line respectively, both the second word line and the third word line comprise word lines physically located on a side of the first word line away from the selected word line, memory cells coupled to the second word line comprise programmed memory cells, memory cells coupled to the third word line comprise unprogrammed memory cells, and the first pass voltage, the second pass voltage and the third pass voltage are all different.

Abstract: Provided herein are nanobodies, polypeptides including the same, and uses thereof. The nanobody's variable region includes 3 complementarity determining regions (CDRs) and framework regions (FRs), where the CDRs are as follows: CDR1: Ser-Gly-Xaa11-Xaa12-Phe-Xaa13-Xaa14-Asn-Xaa15 (Formula I); CDR2: Xaa21-Thr-Xaa22-Xaa23-Gly-Xaa24-Thr (Formula II); CDR3: His-Xaa31-Asp-Glu-Xaa32-Arg-Xaa33-Ser-Xaa34-Trp-Thr-Thr-Ser-Asn-Xaa35 (Formula III). The nanobodies and their polypeptides exhibit high affinity and activity, specifically recognizing and binding AAV. Affinity agents prepared therefrom have strong AAV adsorption capacity, suitable for AAV affinity chromatography to facilitate its industrial application. They are also applicable to AAV detection, enabling simultaneous detection of empty capsids and viral particles.

Abstract: The present disclosure provides a semiconductor device, system, and an operating method thereof. The semiconductor device includes a peripheral circuit and an array of memory cells. The array of memory cells is coupled to the peripheral circuit, and includes a storage zone and a compute-in-memory zone. The compute-in-memory zone includes a plurality of memory banks, the storage zone and any one of the memory banks includes a plurality of memory blocks. The plurality of memory banks are configured to perform a compute-in-memory operation. The plurality of memory blocks in the storage zone are configured to perform a memory operation.

Abstract: The present application provides a memory system, a method for operating the memory system, a controller and a storage medium. The memory system includes: a memory device and a controller; the controller is configured to send a read command to the memory device; the memory device is configured to read data stored in a first memory cell in the memory device according to the read command; the first memory cell and the second memory cell are located in the same memory string; the second memory cell is a memory cell that has not yet been written with data; the controller is further configured to send a write command to the memory device; the memory device is further configured to write data read from the first memory cell to the second memory cell according to the write command.

Abstract: A device and a driving method for driving a microfluidic chip are disclosed. The device for driving a microfluidic chip includes a carrying member configured to carry the microfluidic chip; a releasing member configured to electrically connected to the microfluidic chip, and control the release of the reagent of the microfluidic chip, a valve control member configured to control the opening and closing of the flow channel in the valve control area of the microfluidic chip when the valve control area is within the valve control range of the valve control member, a fluid driving member configured to drive the flow of fluid in the microfluidic chip, and a controller configured to control the driving process of the microfluidic chip.

Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to determine an update function based on data indicating pressure in a tire of a vehicle over a most-recent time period, determine a current test statistic for the most-recent time period, and, in response to the current test statistic exceeding a threshold, output a message indicating low pressure of the tire. The update function lacks an input of temperature. The current test statistic is a function of the update function and a previous test statistic. The previous test statistic is for an immediately previous time period from the most-recent time period.

Abstract: A thermal control system is configured to transfer heat between refrigerant and coolant. A coolant distribution system includes one or more pumps and valves that are configured to control coolant flow to selectively heat and/or cool a vehicle cabin and/or vehicle components. Measured pump and valve operating parameters may be utilized to repeatedly update metrics that model the states of the pumps and/or valves. Anomalies may be detected by comparing the updated metrics to expected metrics. An alert concerning impending operating issue may be provided based, at least in part, on detected anomalies. A remaining useful life (RUL) of the pumps and/or valves may be determined based, at least in part, on detected anomalies.

Abstract: A method and technique for restraining an aggressive artificial intelligence robot dog, using a drone to deploy a stainless-steel wire ring chain that immobilizes the robot dog upon contact by wrapping around the robot dog's legs and body, and includes a retrieval system for capturing the immobilized robot dog for tactical or security purposes.

Abstract: A metal-containing photoresist film may be deposited on a semiconductor substrate using a dry deposition technique. Unintended metal-containing photoresist material may form on internal surfaces of a process chamber during deposition, bevel and backside cleaning, baking, development, or etch operations. An in situ dry chamber clean may be performed to remove the unintended metal-containing photoresist material by exposure to an etch gas. The dry chamber clean may be performed at elevated temperatures without striking a plasma. In some embodiments, the dry chamber clean may include pumping/purging and conditioning operations.

Abstract: The present disclosure provides a semiconductor device and an operating method thereof, and a system. The semiconductor device includes a memory cell array, word lines coupled to the memory cell array, and a peripheral circuit coupled to the word lines, wherein the peripheral circuit is configured to: perform a first program operation on a target memory cell set of a plurality of memory cell sets coupled to a selected word line, wherein the first program operation includes a plurality of first program cycles; and the target memory cell set includes a plurality of memory cells whose threshold voltages are to be programmed into a target threshold voltage distribution; and perform a second program operation on the target memory cell set, wherein the second program operation includes at least one second program cycle, the second program cycle includes a verify phase and a program phase after the verify phase.