Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, and applying, to a second word line, a first pass voltage during a first stage of the first loop and a second pass voltage during a second stage of the first loop. The method further includes, during a second loop of the program operation, applying a second program voltage to the first word line, and applying, to the second word line, a third pass voltage during a first stage of the second loop and a fourth pass voltage during a second stage of the second loop. A difference between the fourth pass voltage and the third pass voltage is greater than a difference between the second pass voltage and the first pass voltage.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, applying, to a second word line, a first pass voltage during a first stage and a second pass voltage during a second stage; during a second loop, applying a second program voltage to the first word line, applying, to the second word line, a third pass voltage during a first stage and a fourth pass voltage during a second stage; and during a third loop, applying a third program voltage to the first word line, applying, to the second word line, a fifth pass voltage during a first stage and a sixth pass voltage during a second stage. The third pass voltage is lower than the first pass voltage and the fifth pass voltage.

Abstract: The present application provides memory devices, operating methods, and memory systems. An example memory device includes: a first, second, and third top select line, multiple word lines, multiple memory cells, and a peripheral circuit configured to: in a process of programming the multiple memory cells coupled to a selected word line of the multiple word lines, dynamically adjust an application approach of a select voltage on the second top select line depending on a distance between the selected word line and the third top select line; wherein when the first top select line reaches its select voltage is different from when the third top select line reaches its select voltage, and when the second top select line reaches its select voltage is not earlier than when the first top select line reaches its select voltage and not later than when the third top select line reaches its select voltage.

Abstract: Dry backside and bevel edge clean is performed without exposure to plasma to remove unwanted photoresist material from a substrate. The substrate is supported on a substrate support and elevated by minimum contact area (MCA) supports so that etch gas can access a backside of the substrate. A gas distributor delivers curtain gas to a frontside of the substrate to protect photoresist material on the frontside. An etch gas delivery source delivers a first etch gas flow to the backside, and one or more peripheral gas inlets deliver a second etch gas flow to a periphery of the frontside and around the bevel edge. A radiative heat source is positioned below the substrate to heat the substrate.

Abstract: Some examples of the present disclosure provide a semiconductor device. The semiconductor device comprises first and second semiconductor structures bonded to each other. The first semiconductor structure includes a memory array, a peripheral circuit coupled to the memory array, and a first bonding contact, a second bonding contact and a third bonding contact respectively coupled to the peripheral circuit, and the second semiconductor structure comprises a control circuit, an analog-to-digital conversion circuit coupled to the control circuit, a fourth bonding contact and a fifth bonding contact respectively coupled to the control circuit, and a sixth bonding contact coupled to the analog-to-digital conversion circuit. Various channels are formed between different bonding contacts to transmit different information.

Abstract: A method using a pair of user devices formed of a teacher user device and a student user device where the student device uses the ML model for a task is provided. A method performed by the teacher device may include receiving, from the student device of the pair of user devices, at least one captured data item and a request for a student machine learning model to be updated, where the student ML model is stored on the student device and is to be used by the student device. The method may include updating, using the received at least one captured data item, a subset of a plurality of parameters of a copy of the student machine learning model that is stored on the teacher device. The method may include transmitting the updated subset of parameters to the student device for updating the student ML model.

Abstract: A power tool includes a cylinder at least partially disposed in a housing, where gas is stored in the cylinder. The cylinder includes: an inflation nozzle, where the cylinder is inflated with the gas in advance through the inflation nozzle; an inflation valve, where the gas filled through the inflation nozzle flows through the inflation valve and then enters the cylinder; and a pressure relief valve disposed between the inflation nozzle and the inflation valve, where when a pressure of the gas filled through the inflation nozzle is greater than a first preset pressure, the filled gas is released through the pressure relief valve.

Abstract: Provided are a base station (100) and a cleaning system. The base station (100) contains: a base station body (110), a washing disk (120) and a dust collection assembly, wherein the washing disk (120) is located at a lower part of the base station body (110), and the washing disk (120) is provided with a sink (121) and a dirt outlet (122); the dust collection assembly is located in the base station body (110) and includes a dust collection box (160), a dust collection pipeline and a first fan (170); and the dirt outlet (122) is in communication with the dust collection box (160) via the dust collection pipeline. In a first working mode of the dust collection pipeline, power generated by the first fan (170) delivers dirt in the sink (120) to the dust collection box (160) via the dirt outlet (122) and the dust collection pipeline.

Abstract: A semiconductor device includes a transistor and an isolation structure. The transistor includes a semiconductor body extending along a first direction and a gate structure coupled with the semiconductor body in a second direction perpendicular to the first direction. The isolation structure is located adjacent to the semiconductor body. The isolation structure includes a first portion extending along the first direction and having at least one air gap therein and a second portion connected with a first end of the first portion along the first direction. The second portion is solid, and a size of the second portion in the reference plane is smaller than a size of the first portion in the reference plane.

Abstract: The present application provides a memory system, a method for operating the memory system, a controller and a storage medium. The memory system includes: a memory device and a controller; the controller is configured to send a read command to the memory device; the memory device is configured to read data stored in a first memory cell in the memory device according to the read command; the first memory cell and the second memory cell are located in the same memory string; the second memory cell is a memory cell that has not yet been written with data; the controller is further configured to send a write command to the memory device; the memory device is further configured to write data read from the first memory cell to the second memory cell according to the write command.

Abstract: Various techniques for controlling metal-containing contamination on a semiconductor substrate are provided herein. Such techniques may involve one or more of a post-development bake treatment, a chemical treatment, a plasma treatment, a light treatment, and a backside and bevel edge clean. The techniques may be combined as desired for a particular application. In many cases, the techniques are used to address metal-containing contamination that is generated during a photoresist development operation.

Abstract: An example memory device includes: a memory cell array, a plurality of word lines, and a peripheral circuit configured to: apply a first verification voltage to a selected word line, where a plurality of memory cells connected to the selected word line includes a first group of memory cells and a second group of memory cells, threshold voltages for first memory cells in the first group of memory cells are smaller than the first verification voltage, and threshold voltages for second memory cells in the second group of memory cells are greater than or equal to the first verification voltage; and perform a program operation on at least a portion of the first memory cells in the first group of memory cells and the second memory cells in the second group of memory cells. Threshold voltages corresponding to the target memory states are smaller than the first verification voltage.

Abstract: Systems, devices, and methods for manufacturing and operating a ferroelectric memory device are provided. In one aspect, a semiconductor device includes a ferroelectric memory cell, including: a first conductive layer; a dielectric layer in contact with the first conductive layer; a channel layer in contact with the dielectric layer; a ferroelectric layer in contact with the channel layer; and a second conductive layer in contact with the ferroelectric layer, where the channel layer is between the first conductive layer and the second conductive layer, and the ferroelectric layer is between the channel layer and the second conductive layer.

Abstract: Systems, devices, and methods for manufacturing and operating a ferroelectric memory device are provided. In one aspect, a method of operating a ferroelectric memory device includes: performing a program operation on a first ferroelectric memory cell, including: applying a program voltage to a first word line coupled to the first ferroelectric memory cell; applying a pass voltage to a second word line coupled to a second ferroelectric memory cell; applying a first voltage to a selected top select gate (TSG); and applying a second voltage greater than the first voltage to an unselected TSG.

Abstract: The present disclosure relates to stacks having a sensitized resist film, as well as methods and apparatuses for applying such sensitized films. In particular embodiments, the sensitizer can be provided in gas form, and unreacted sensitizer precursors can be recovered after a deposition step.

Abstract: A metal-containing photoresist film may be deposited on a semiconductor substrate using a dry deposition technique. Unintended metal-containing photoresist material may form on internal surfaces of a process chamber during deposition, bevel and backside cleaning, baking, development, or etch operations. An in situ dry chamber clean may be performed to remove the unintended metal-containing photoresist material by exposure to an etch gas. The dry chamber clean may be performed at elevated temperatures without striking a plasma. In some embodiments, the dry chamber clean may include pumping/purging and conditioning operations.

Abstract: Systems, devices, and methods for operating a ferroelectric device are provided. In one aspect, a method of operating a ferroelectric memory device includes: performing, during a first phase, a program operation on a first ferroelectric memory cell, including: applying a program voltage to a first word line coupled to the first ferroelectric memory cell, and applying a pass voltage to a second word line coupled to a second ferroelectric memory cell; and performing, during a second phase after the first phase, a second operation, including: applying a first voltage to the second word line; applying a second voltage to a source line; and applying a third voltage to a bit line. At least one of the second voltage or the third voltage is greater than the first voltage.

Abstract: A method includes discharging a voltage of a first word line to a first voltage after performing a first read operation on a first memory cell; floating the first word line after discharging the voltage of the first word line to the first voltage; applying a second voltage to the first word line in a first phase of performing a second read operation on the first memory cell, wherein the second read operation is after floating the first word line, and the second voltage is greater than the first voltage; and applying a pre pulse voltage to the first word line in a second phase of performing the second read operation, wherein the second phase is after the first phase, and the pre pulse voltage is greater than the second voltage.

Abstract: Methods, devices, and systems for managing program operations are provided. In one aspect, a memory system includes a memory device, and a memory controller coupled to the memory device. The memory controller is configured to instruct the memory device to write first data in a first single-level cell (SLC) mode using a first program pulse, and in response to detecting that the memory system is disconnected from an external power source, instruct the memory device to write second data in a second SLC mode using a second program pulse. The second program pulse is different from the first program pulse.

Abstract: The present disclosure provides a semiconductor device including a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory banks, and each of the memory banks includes at least one memory block in a first type of program state; the peripheral circuit writes data of at least one first memory block into at least one second memory block to obtain the second memory block in a second type of program state. The first memory block and the second memory block are different memory blocks in memory blocks of a target memory bank, and the first memory block includes a memory block in the first type of program state; and erase data of the first memory block, until each memory block in the first type of program state in the target memory bank is erased once.