Abstract: In some examples, a peripheral circuit is configured to: when performing a first read operation on memory cells coupled to a selected word line, apply a first pass voltage to a first word line, apply a second pass voltage to a second word line, and apply a third pass voltage to a third word line, wherein the first word line comprises at least one word line physically located above and below the selected word line respectively, both the second word line and the third word line comprise word lines physically located on a side of the first word line away from the selected word line, memory cells coupled to the second word line comprise programmed memory cells, memory cells coupled to the third word line comprise unprogrammed memory cells, and the first pass voltage, the second pass voltage and the third pass voltage are all different.

Abstract: Provided herein are nanobodies, polypeptides including the same, and uses thereof. The nanobody's variable region includes 3 complementarity determining regions (CDRs) and framework regions (FRs), where the CDRs are as follows: CDR1: Ser-Gly-Xaa11-Xaa12-Phe-Xaa13-Xaa14-Asn-Xaa15 (Formula I); CDR2: Xaa21-Thr-Xaa22-Xaa23-Gly-Xaa24-Thr (Formula II); CDR3: His-Xaa31-Asp-Glu-Xaa32-Arg-Xaa33-Ser-Xaa34-Trp-Thr-Thr-Ser-Asn-Xaa35 (Formula III). The nanobodies and their polypeptides exhibit high affinity and activity, specifically recognizing and binding AAV. Affinity agents prepared therefrom have strong AAV adsorption capacity, suitable for AAV affinity chromatography to facilitate its industrial application. They are also applicable to AAV detection, enabling simultaneous detection of empty capsids and viral particles.

Abstract: The present disclosure provides a semiconductor device, system, and an operating method thereof. The semiconductor device includes a peripheral circuit and an array of memory cells. The array of memory cells is coupled to the peripheral circuit, and includes a storage zone and a compute-in-memory zone. The compute-in-memory zone includes a plurality of memory banks, the storage zone and any one of the memory banks includes a plurality of memory blocks. The plurality of memory banks are configured to perform a compute-in-memory operation. The plurality of memory blocks in the storage zone are configured to perform a memory operation.

Abstract: The present application provides a memory system, a method for operating the memory system, a controller and a storage medium. The memory system includes: a memory device and a controller; the controller is configured to send a read command to the memory device; the memory device is configured to read data stored in a first memory cell in the memory device according to the read command; the first memory cell and the second memory cell are located in the same memory string; the second memory cell is a memory cell that has not yet been written with data; the controller is further configured to send a write command to the memory device; the memory device is further configured to write data read from the first memory cell to the second memory cell according to the write command.

Abstract: A device and a driving method for driving a microfluidic chip are disclosed. The device for driving a microfluidic chip includes a carrying member configured to carry the microfluidic chip; a releasing member configured to electrically connected to the microfluidic chip, and control the release of the reagent of the microfluidic chip, a valve control member configured to control the opening and closing of the flow channel in the valve control area of the microfluidic chip when the valve control area is within the valve control range of the valve control member, a fluid driving member configured to drive the flow of fluid in the microfluidic chip, and a controller configured to control the driving process of the microfluidic chip.

Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to determine an update function based on data indicating pressure in a tire of a vehicle over a most-recent time period, determine a current test statistic for the most-recent time period, and, in response to the current test statistic exceeding a threshold, output a message indicating low pressure of the tire. The update function lacks an input of temperature. The current test statistic is a function of the update function and a previous test statistic. The previous test statistic is for an immediately previous time period from the most-recent time period.

Abstract: A thermal control system is configured to transfer heat between refrigerant and coolant. A coolant distribution system includes one or more pumps and valves that are configured to control coolant flow to selectively heat and/or cool a vehicle cabin and/or vehicle components. Measured pump and valve operating parameters may be utilized to repeatedly update metrics that model the states of the pumps and/or valves. Anomalies may be detected by comparing the updated metrics to expected metrics. An alert concerning impending operating issue may be provided based, at least in part, on detected anomalies. A remaining useful life (RUL) of the pumps and/or valves may be determined based, at least in part, on detected anomalies.

Abstract: A method and technique for restraining an aggressive artificial intelligence robot dog, using a drone to deploy a stainless-steel wire ring chain that immobilizes the robot dog upon contact by wrapping around the robot dog's legs and body, and includes a retrieval system for capturing the immobilized robot dog for tactical or security purposes.

Abstract: A metal-containing photoresist film may be deposited on a semiconductor substrate using a dry deposition technique. Unintended metal-containing photoresist material may form on internal surfaces of a process chamber during deposition, bevel and backside cleaning, baking, development, or etch operations. An in situ dry chamber clean may be performed to remove the unintended metal-containing photoresist material by exposure to an etch gas. The dry chamber clean may be performed at elevated temperatures without striking a plasma. In some embodiments, the dry chamber clean may include pumping/purging and conditioning operations.

Abstract: The present disclosure provides a semiconductor device and an operating method thereof, and a system. The semiconductor device includes a memory cell array, word lines coupled to the memory cell array, and a peripheral circuit coupled to the word lines, wherein the peripheral circuit is configured to: perform a first program operation on a target memory cell set of a plurality of memory cell sets coupled to a selected word line, wherein the first program operation includes a plurality of first program cycles; and the target memory cell set includes a plurality of memory cells whose threshold voltages are to be programmed into a target threshold voltage distribution; and perform a second program operation on the target memory cell set, wherein the second program operation includes at least one second program cycle, the second program cycle includes a verify phase and a program phase after the verify phase.

Abstract: An example method of operating a memory device includes performing a program operation on a first memory cell in a first program operation phase and performing a program operation on a second memory cell and applying a program-inhibiting voltage to a first bit line coupled to the first memory cell in a second program operation phase. The first memory cell and the second memory cell are coupled to a same word line. A target threshold voltage of the first memory cell is greater than a target threshold voltage of the second memory cell. The first program operation phase precedes the second program operation phase.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a peripheral circuit. The semiconductor device may include a memory cell array. The peripheral circuit may be coupled to the memory cell array, the memory cell array may include a plurality of memory regions, and each memory region may include a first number of memory blocks. The peripheral circuit may be configured to receive an operation instruction. The operation instruction may include address information for determining a target memory region in the plurality of memory regions and a second number of working memory blocks in the target memory region. The second number may be less than the first number. The peripheral circuit may be configured to perform a corresponding operation on the working memory blocks in response to the operation instruction.

Abstract: A battery pack includes multiple cells; a cell bracket configured to support the multiple cells; and a terminal assembly electrically connected to the multiple cells and configured to be coupled to an interface of a power tool. The cell bracket is at least partially exposed to an external environment, and the thermal conductivity of the cell bracket is higher than or equal to 0.5 W/(m·K). The temperature of the battery pack can be accurately detected, the cycling efficiency of the battery pack is ensured, and the risk of explosion caused by thermal runaway of the battery can be eliminated.

Abstract: A motor vehicle includes a heat pump with an expansion valve and a controller that is configured to control a position of the expansion valve based, at least in part, on a superheat target, and utilize differences between an expected position of the expansion valve and a controlled position of the expansion valve to estimate a refrigerant level of the heat pump and/or a remaining useful life of the heat pump. The controller is optionally configured to determine a plurality of estimated refrigerant levels during closed loop control of the heat pump system and utilize the plurality of estimated refrigerant levels to determine a trend in refrigerant level over time.

Abstract: A disclosed semiconductor device comprises a first semiconductor structure comprising an analog-to-digital converter circuit and a data processing circuit; and a second semiconductor structure comprising a memory array and a peripheral circuit coupled to the memory array; wherein the analog-to-digital converter circuit is coupled with the memory array and configured to convert analog computation information based on a first operation performed by the memory array into digital information, and the data processing circuit is coupled with the analog-to-digital converter circuit and configured to perform a second operation based on the digital information.

Abstract: The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.

Abstract: Process condition management facilitates the combination of dry development and post-development treatment into a single process chamber, eliminating the necessity for a post-dry development bake step in a separate chamber during semiconductor manufacturing. Thermal dry development and plasma dry development may be performed in the same chamber. Thermal dry development, plasma dry development and passivation such as an O2 flash treatment; or thermal dry development, plasma dry development, passivation and hardening operations are enabled without wafer transfer.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, applying, to a second word line, a first pass voltage during a first stage and a second pass voltage during a second stage; during a second loop, applying a second program voltage to the first word line, applying, to the second word line, a third pass voltage during a first stage and a fourth pass voltage during a second stage; and during a third loop, applying a third program voltage to the first word line, applying, to the second word line, a fifth pass voltage during a first stage and a sixth pass voltage during a second stage. The third pass voltage is lower than the first pass voltage and the fifth pass voltage.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a memory array comprising a first memory string and a second memory string. The first memory string may include at least one first dummy memory cell. The semiconductor device may include a peripheral circuit coupled to the memory array and configured to perform a program operation on the at least one first dummy memory cell, such that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold. In a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, a difference between a current of the first memory string and a current of the second memory string may be less than or equal to a preset threshold.

Abstract: Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, and applying, to a second word line, a first pass voltage during a first stage of the first loop and a second pass voltage during a second stage of the first loop. The method further includes, during a second loop of the program operation, applying a second program voltage to the first word line, and applying, to the second word line, a third pass voltage during a first stage of the second loop and a fourth pass voltage during a second stage of the second loop. A difference between the fourth pass voltage and the third pass voltage is greater than a difference between the second pass voltage and the first pass voltage.