Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier.

Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.

Abstract: In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.

Abstract: Semiconductor memory devices and a method thereof are provided. An example semiconductor memory device may include a control signal generation unit configured to generate a plurality of control signals in response to a bias current, a reference current generation unit configured to generate a reference current in response to the plurality of control signals and a sense amplifier configured to sense and amplify data stored in a given memory cell based on the reference current and a current on a bit line connected to the memory cell.

Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.

Abstract: A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a reference cell current flows between a drain and a source based on a bias voltage, an internal bias current generator configured to generate an internal bias current capable of being trimmed, and a trimming circuit configured to trim the reference cell based on the internal bias current.

Abstract: A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

Abstract: Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.

Abstract: A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation is performed on erased memory cells having a threshold voltage lower than a second program verify voltage. The second program verify voltage is lower than the first program verify voltage.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.

Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier.

Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.

Abstract: A high voltage regulator may include a first regulating unit, a second regulating unit, and an output node. The first regulating unit regulates the program voltage in a voltage-level-up interval of a program voltage of a memory cell. The second regulating unit regulates the program voltage in a voltage-level-down interval of the program voltage. The output node outputs the regulated program voltage.

Abstract: In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.

Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.

Abstract: The invention relates to a voltage regulator for operation of a semiconductor memory device. In embodiments, the voltage regulator includes a standby regulator unit and an active regulating unit. Embodiments of the invention decouple the operation of the standby regulating unit and the active regulating unit of a voltage regulator so that both can operate simultaneously, for example during a read operation. In embodiments of the invention, the standby regulating unit includes a short pulse generator and a feedback loop to disable the standby regulating unit for a predetermined amount of time.

Abstract: Semiconductor memory devices and a method thereof are provided. An example semiconductor memory device may include a control signal generation unit configured to generate a plurality of control signals in response to a bias current, a reference current generation unit configured to generate a reference current in response to the plurality of control signals and a sense amplifier configured to sense and amplify data stored in a given memory cell based on the reference current and a current on a bit line connected to the memory cell.

Abstract: A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation is performed on erased memory cells having a threshold voltage lower than a second program verify voltage. The second program verify voltage is lower than the first program verify voltage.

Abstract: A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a reference cell current flows between a drain and a source based on a bias voltage, an internal bias current generator configured to generate an internal bias current capable of being trimmed, and a trimming circuit configured to trim the reference cell based on the internal bias current.

Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.