Abstract: The present invention relates to a circuit for clamping a word line voltage. The circuit comprises a reference voltage generating means for generating a reference voltage depending on first and second signals; a bootstrap circuit for generating a pumping voltage of a higher potential than a target voltage depending on the first and second signals to an output terminal; a control signal generating means for generating the first and second control signals depending on the first˜third signals; a clamping control means for falling the pumping voltage depending the first and second control signals to generate a compare voltage; a comparator for comparing the reference voltage and the compare voltage to generate a third signal; and a discharging means for discharging the potential of the output terminal depending on the third signal to fall the pumping voltage to a target voltage.

Abstract: A sensing circuit of a non-volatile memory device comprises a regulation unit, a DTMOS transistor, a first NMOS transistor, a second NMOS transistor and a sense amplifier. The sensing circuit of the present invention eliminates the threshold voltage on the high voltage transistor; therefore, the sensing circuit prevents gate oxide breakdown, makes it possible to drive the sensing circuit using a low voltage, and increases processing speed by improving transconductance.

Abstract: The nonvolatile memory sensing circuit includes a main cell part and at least one reference cell part, including a main cell array having a plurality of main cells to which a word line driving signal is applied respectively, a plurality of main cell switches receiving a plurality of main cell selection signals YG0 to YGn which switch to select one of the main cells wherein the main cell switches are connected to the main cell array in series, a main cell bit line voltage controller maintaining drain voltage to a fixed level by receiving program bias voltage PRBIAS, a main cell path transistor connected between an output of the main cell bit line voltage controller and internal power supply voltage wherein the main cell path transistor outputting a state of the main cell, and at least one sense amplifier producing a comparison output SAOUT by receiving at least one reference voltage RDREF and an output SENSE of the main cell path transistor, and wherein the reference cell part further comprises a program refer

Abstract: The present invention relates to semiconductor memory, more particularly, to nonvolatile memory sensing circuits and techniques thereof which improves the reference structure therein.

Abstract: The nonvolatile memory sensing circuit includes a main cell part and at least one reference cell part, including a main cell array having a plurality of main cells to which a word line driving signal is applied respectively, a plurality of main cell switches receiving a plurality of main cell selection signals YG0 to YGn which switch to select one of the main cells wherein the main cell switches are connected to the main cell array in series, a main cell bit line voltage controller maintaining drain voltage to a fixed level by receiving program bias voltage PRBIAS, a main cell path transistor connected between an output of the main cell bit line voltage controller and internal power supply voltage wherein the main cell path transistor outputting a state of the main cell, and at least one sense amplifier producing a comparison output SAOUT by receiving at least one reference voltage RDREF and an output SENSE of the main cell path transistor, and wherein the reference cell part further comprises a program refer

Abstract: A redundancy fuse read circuit includes an external source voltage detector for detecting a voltage level of an external source voltage and generating a HIGH enable detection signal, a fuse information storage unit for generating fuse information by capacitive coupling in accordance with the HIGH enable detection signal and for sensing the fuse information, and a comparator for comparing an output signal of the fuse information storage unit and one of an internal and external address signals.