Abstract: A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.

Abstract: A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.

Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier.

Abstract: A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier.

Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.

Abstract: A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.

Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier.

Abstract: A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.

Abstract: The present invention relates to a clamp circuit and a boosting circuit using the same. In order to drop a boosting voltage to a target word line voltage, at least one or more clamp circuit is provided. At least one or more of the clamp circuits are independently driven in a desired sensing period to lower the boosting voltage. Thus, rapid read access time is accomplished upon a data read operation. Current consumption can be minimized and a stabilized word line voltage can be generated.

Abstract: The present invention relates to a clamping circuit and a nonvolatile memory device using the same. Each of switching means driven by a gate voltage of a transistor included in a clamping circuit are installed between a drain terminal of the transistor and a terminal of the well in which the transistor is formed. A given bias is applied to the well and the threshold voltage of the transistor is thus lowered. Thus, the operating speed of the transistor can be increased even at a low power supply voltage without additionally using a manufacture process for the low voltage operation. Further, the ripple voltage can be minimized and generation of defect can be thus prevented. As a result, electrical characteristic and reliability of the circuit is improved.

Abstract: The present invention relates to a boosting circuit. A boosting voltage (VBOOT) is dropped to a given voltage level through a pre-select clamp circuit and the boosting voltage (VBOOT) is again dropped through a clamp circuit, depending on the power supply voltage, so that a final target word line voltage is generated. Accordingly, a read access time is rapid upon a read operation, the current consumption is minimized and a stabilized word line voltage can be generated.

Abstract: A sensing circuit of a non-volatile memory device comprises a regulation unit, a DTMOS transistor, a first NMOS transistor, a second NMOS transistor and a sense amplifier. The sensing circuit of the present invention eliminates the threshold voltage on the high voltage transistor; therefore, the sensing circuit prevents gate oxide breakdown, makes it possible to drive the sensing circuit using a low voltage, and increases processing speed by improving transconductance.

Abstract: The present invention relates to a clamp circuit and a boosting circuit using the same. In order to drop a boosting voltage to a target word line voltage, at least one or more clamp circuit is provided. At least one or more of the clamp circuits are independently driven in a desired sensing period to lower the boosting voltage. Thus, rapid read access time is accomplished upon a data read operation. Current consumption can be minimized and a stabilized word line voltage can be generated.

Abstract: The present invention relates to a boosting circuit. A boosting voltage (VBOOT) is dropped to a given voltage level through a pre-select clamp circuit and the boosting voltage (VBOOT) is again dropped through a clamp circuit, depending on the power supply voltage, so that a final target word line voltage is generated. Accordingly, a read access time is rapid upon a read operation, the current consumption is minimized and a stabilized word line voltage can be generated.

Abstract: The present invention relates to a clamping circuit and a nonvolatile memory device using the same. Each of switching means driven by a gate voltage of a transistor included in a clamping circuit are installed between a drain terminal of the transistor and a terminal of the well in which the transistor is formed. A given bias is applied to the well and the threshold voltage of the transistor is thus lowered. Thus, the operating speed of the transistor can be increased even at a low power supply voltage without additionally using a manufacture process for the low voltage operation. Further, the ripple voltage can be minimized and generation of defect can be thus prevented. As a result, electrical characteristic and reliability of the circuit is improved.

Abstract: The present invention relates to a supply voltage level detector. The supply voltage level detector includes a reference voltage generator for generating the reference voltage of a constant level depending on a control signal, a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal, and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal. The present invention constructs the compare voltage generator in the supply voltage level detector so that the variation of the compare voltage depending on the variation of the supply voltage becomes great. Therefore, the present invention can improve the sensing margin of the comparator for sensing the difference between the reference voltage and the compare voltage. Also, the present invention can prevent erroneous operation by a noise to accomplish a stable operation.

Abstract: The present invention relates to a supply voltage level detector. The supply voltage level detector includes a reference voltage generator for generating the reference voltage of a constant level depending on a control signal, a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal, and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal. The present invention constructs the compare voltage generator in the supply voltage level detector so that the variation of the compare voltage depending on the variation of the supply voltage becomes great. Therefore, the present invention can improve the sensing margin of the comparator for sensing the difference between the reference voltage and the compare voltage. Also, the present invention can prevent erroneous operation by a noise to accomplish a stable operation.

Abstract: The present invention relates to a circuit for clamping a word line voltage. The circuit comprises a reference voltage generating means for generating a reference voltage depending on first and second signals; a bootstrap circuit for generating a pumping voltage of a higher potential than a target voltage depending on the first and second signals to an output terminal; a control signal generating means for generating the first and second control signals depending on the first˜third signals; a clamping control means for falling the pumping voltage depending the first and second control signals to generate a compare voltage; a comparator for comparing the reference voltage and the compare voltage to generate a third signal; and a discharging means for discharging the potential of the output terminal depending on the third signal to fall the pumping voltage to a target voltage.