Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.

Abstract: The memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.

Abstract: A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.

Abstract: A method of operating a memory device to read data may include determining, in a first read interval associated with a first read operation, a threshold voltage distribution of a most significant program state of a target logical memory page included in a first physical memory page among a plurality of physical memory pages, the first read operation being an operation of reading the target logical memory page of the first physical memory page; transmitting, to a memory controller, a distribution determination result, the distribution determination result being related to the threshold voltage distribution; receiving, from the memory controller, offset levels corrected based on the distribution determination result; and adjusting a read voltage based on offset levels prior to performing a second read operation on a second physical memory page among the plurality of physical memory pages.

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells; a page buffer for performing a plurality of read operations and storing results of the read operations, wherein each of the read operations includes at least one sensing operation for selected memory cells from the plurality of memory cells; a multi-sensing manager for determining a number of sensing operations for each of the plurality of read operations and controlling the page buffer to perform the read operations; and a data identifier for identifying a data state of a bit for the selected memory cells based on the results of the read operations, wherein the multi-sensing manager determines the number of sensing operations for at least one read operation from among the read operations to be different from the number of sensing operations for other read operations from among the read operations.

Abstract: A method of operating a memory device to read data may include determining, in a first read interval associated with a first read operation, a threshold voltage distribution of a most significant program state of a target logical memory page included in a first physical memory page among a plurality of physical memory pages, the first read operation being an operation of reading the target logical memory page of the first physical memory page; transmitting, to a memory controller, a distribution determination result, the distribution determination result being related to the threshold voltage distribution; receiving, from the memory controller, offset levels corrected based on the distribution determination result; and adjusting a read voltage based on offset levels prior to performing a second read operation on a second physical memory page among the plurality of physical memory pages.

Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.

Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.

Abstract: Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.

Abstract: Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.