Abstract: A semiconductor device includes a substrate including cell and dummy regions, first channel structures on the cell region and extending in a first direction vertical with respect to the substrate, gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the substrate, the gate lines being spaced apart from each other along the first direction, cutting lines between the gate lines on the cell region and extending in the second direction, dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that in the gate lines, and dummy lines through the dummy patterns.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: Provided are a non-volatile memory device, a memory system, and a method of operating the non-volatile memory device. The method includes: performing a user operation according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to a memory cell array; setting up voltages of a plurality of word lines; floating at least one word line from among the plurality of word lines, the voltages of which are set up, according to the at least one selected mode; and detecting whether the at least one word line has a progressive defect, according to a result of detecting a voltage level of the at least one floated word line.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.

Abstract: An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal.

Abstract: Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array.

Abstract: A resistive memory device comprising: a memory cell having a programmable resistance representing stored data; and a read circuit configured to be connected to the memory cell via a first signal line and read the stored data, wherein the read circuit includes: a voltage controller configured to control a first voltage of the first signal line to be a constant voltage and output a signal to a sensing node; and a sense amplifier connected to the voltage controller via the sensing node, and configured to compare a sensing voltage of the sensing node with a reference voltage.

Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract: A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.

Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.

Abstract: In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.

Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.