Patents by Inventor Dae-Seok Byeon

Dae-Seok Byeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20160027510
    Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
    Type: Application
    Filed: April 27, 2015
    Publication date: January 28, 2016
    Inventors: YONG-KYU LEE, DAE-SEOK BYEON, YEONG-TAEK LEE, CHI-WEON YOON, HYUN-KOOK PARK, HYO-JIN KWON
  • RESISTIVE MEMORY DEVICE AND OPERATION
    Publication number: 20160027508
    Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
    Type: Application
    Filed: February 25, 2015
    Publication date: January 28, 2016
    Inventors: YONG-KYU LEE, DAE-SEOK BYEON, HYO-JIN KWON, HYUN-KOOK PARK, CHI-WEON YOON, YEONG-TAEK LEE
  • RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE
    Publication number: 20160019951
    Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.
    Type: Application
    Filed: March 23, 2015
    Publication date: January 21, 2016
    Inventors: HYUN-KOOK PARK, DAE-SEOK BYEON, YEONG-TAEK LEE, BO-GEUN KIM, YONG-KYU LEE, HYO-JIN KWON
  • RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20160012890
    Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.
    Type: Application
    Filed: March 12, 2015
    Publication date: January 14, 2016
    Inventors: HYUN-KOOK PARK, DAE-SEOK BYEON, YEONG-TAEK LEE, HYO-JIN KWON, YONG-KYU LEE
  • RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY, AND OPERATING METHOD OF THE RESISTIVE MEMORY DEVICE
    Publication number: 20160005463
    Abstract: An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal.
    Type: Application
    Filed: April 27, 2015
    Publication date: January 7, 2016
    Inventors: HYUN-KOOK PARK, YEONG-TAEK LEE, DAE-SEOK BYEON, YONG-KYU LEE, HYO-JIN KWON
  • Memory system and method of operation thereof
    Patent number: 9230669
    Abstract: A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Kil Jung, Hyung-Gon Kim, Dae-Seok Byeon
  • RESISTIVE MEMORY DEVICE AND METHOD OF WRITING DATA
    Publication number: 20150380085
    Abstract: A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.
    Type: Application
    Filed: March 23, 2015
    Publication date: December 31, 2015
    Inventors: HYUN-KOOK PARK, YEONG-TAEK LEE, DAE-SEOK BYEON, YONG-KYU LEE, HYO-JIN KWON
  • RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE
    Publication number: 20150380086
    Abstract: In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.
    Type: Application
    Filed: April 24, 2015
    Publication date: December 31, 2015
    Inventors: HYUN-KOOK PARK, YEONG-TAEK LEE, DAE-SEOK BYEON, YONG-KYU LEE, HYO-JIN KWON
  • RESISTIVE MEMORY DEVICE AND OPERATING METHOD
    Publication number: 20150363257
    Abstract: Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array.
    Type: Application
    Filed: February 11, 2015
    Publication date: December 17, 2015
    Inventors: HYO-JIN KWON, YEONG-TAEK LEE, DAE-SEOK BYEON, YONG-KYU LEE, HYUN-KOOK PARK
  • MEMORY DEVICE READING AND CONTROL
    Publication number: 20150364188
    Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.
    Type: Application
    Filed: March 18, 2015
    Publication date: December 17, 2015
    Inventors: YONG-KYU LEE, YEONG-TAEK LEE, DAE-SEOK BYEON, HYUN-KOOK PARK, HYO-JIN KWON
  • Nonvolatile memory device and method of operating the same
    Patent number: 9189174
    Abstract: Provided are a nonvolatile memory device and a method for operating the nonvolatile memory device. The method for operating the nonvolatile memory device includes generating a first program voltage, applying the generated first program voltage to a first word line to which a first memory cell is connected for performing a first program operation on the first memory cell, determining whether a number of pulses of a pumping clock signal for generating the first program voltage is greater than or equal to a predetermined critical value n (where n is a natural number), and stopping the performing of the first program operation on the first memory cell when the number of pulses of the pumping clock signal is determined to be greater than or equal to the predetermined critical value n.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: November 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jun Lee, Dae-Seok Byeon
  • Resistive memory device and method of operating the same
    Patent number: 9183932
    Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jin Kwon, Yeong-Taek Lee, Dae-Seok Byeon, Yong-Kyu Lee, Hyun-Kook Park
  • Resistive memory device and method programming same
    Patent number: 9171617
    Abstract: A method of programming memory cells of a resistive memory device includes; applying a first current pulse to each of the plurality of memory cells; applying a second current pulse that increases by a first difference compared to the first current pulse to each of the plurality of memory cells to which the first current pulse is applied; and applying a third current pulse that increases by a second difference compared to the second current pulse to each of the plurality of memory cells to which the second current pulse is applied, wherein the first through third current pulses non-linearly increase, and the second difference is greater than the first difference.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: October 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Yeong-Taek Lee, Dae-Seok Byeon, Yong-Kyu Lee, Hyo-Jin Kwon
  • NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE NON-VOLATILE MEMORY DEVICE
    Publication number: 20150287479
    Abstract: Provided are a non-volatile memory device, a memory system, and a method of operating the non-volatile memory device. The method includes: performing a user operation according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to a memory cell array; setting up voltages of a plurality of word lines; floating at least one word line from among the plurality of word lines, the voltages of which are set up, according to the at least one selected mode; and detecting whether the at least one word line has a progressive defect, according to a result of detecting a voltage level of the at least one floated word line.
    Type: Application
    Filed: February 6, 2015
    Publication date: October 8, 2015
    Inventors: Sang-wan NAM, Byung-gil JEON, Dae-seok BYEON
  • NONVOLATILE MEMORY DEVICE INCLUDING DUMMY WORDLINE, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY SYSTEM
    Publication number: 20150113342
    Abstract: A method of operating a memory system includes reading data of first memory cells, the first memory cells being connected to a first wordline from among a plurality of wordlines, the plurality of wordlines including one or more dummy wordlines and one or more normal wordlines; determining whether the first wordline is one of the one or more dummy wordlines by determining, based on the read data, a number of the first memory cells having a first threshold voltage state, the one or more dummy wordlines being wordlines the memory cells of which have been programmed with dummy data, the one or more normal wordlines being wordlines that are not dummy wordlines; and performing a repair algorithm for correcting an error in the read data, selectively according to a result of the determination.
    Type: Application
    Filed: August 19, 2014
    Publication date: April 23, 2015
    Inventors: Bong-Kil JUNG, Dae-Seok BYEON
  • Memory system and method of operating memory system using soft read voltages
    Patent number: 8923067
    Abstract: A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-seok Byeon, Bo-geun Kim, Jae-woo Park
  • MEMORY SYSTEM AND METHOD OF OPERATION THEREOF
    Publication number: 20140198573
    Abstract: A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Inventors: BONG-KIL JUNG, HYUNG-GON KIM, DAE-SEOK BYEON
  • MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM USING SOFT READ VOLTAGES
    Publication number: 20140153338
    Abstract: A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system.
    Type: Application
    Filed: October 10, 2013
    Publication date: June 5, 2014
    Inventors: Dae-seok Byeon, Bo-geun Kim, Jae-woo Park
  • NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20140032821
    Abstract: Provided are a nonvolatile memory device and a method for operating the nonvolatile memory device. The method for operating the nonvolatile memory device includes generating a first program voltage, applying the generated first program voltage to a first word line to which a first memory cell is connected for performing a first program operation on the first memory cell, determining whether a number of pulses of a pumping clock signal for generating the first program voltage is greater than or equal to a predetermined critical value n (where n is a natural number), and stopping the performing of the first program operation on the first memory cell when the number of pulses of the pumping clock signal is determined to be greater than or equal to the predetermined critical value n.
    Type: Application
    Filed: May 29, 2013
    Publication date: January 30, 2014
    Inventors: HAN-JUN LEE, DAE-SEOK BYEON
  • Stack array structure for a semiconductor memory device
    Patent number: 8461627
    Abstract: In a stack array structure for a semiconductor memory device, a first semiconductor layer includes a plurality of first cell strings, and a second semiconductor including a plurality of second cell strings. Bit-line contact plugs are configured to couple a bit-line to two adjacent first cell strings aligned in series in a bit-line direction, and to further couple the bit-line to two adjacent second cell strings respectively located over the two adjacent first cell strings. Common source line contact plugs are configured to couple a common source line to the two adjacent first cell strings and the two adjacent second cell strings. Pocket p-well contact plugs are located at positions corresponding to a layout of the bit-line plugs and/or common source line plugs, and are configured to couple a pocket p-well line to the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: June 11, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-Seok Byeon