Patents by Inventor Dae-Seok Byeon

Dae-Seok Byeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory devices, memory systems, and related operating methods
    Patent number: 9406359
    Abstract: A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: August 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Yeong-Taek Lee, Dae-Seok Byeon, Chi-Weon Yoon
  • RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20160196876
    Abstract: A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.
    Type: Application
    Filed: December 28, 2015
    Publication date: July 7, 2016
    Inventors: YONG-KYU LEE, YEONG-TAEK LEE, DAE-SEOK BYEON, CHI-WEON YOON
  • Memory device and method of operating the same
    Patent number: 9384832
    Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jin Kwon, Yeong-Taek Lee, Dae-Seok Byeon
  • Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system
    Patent number: 9367417
    Abstract: A method of operating a memory system includes reading data of first memory cells, the first memory cells being connected to a first wordline from among a plurality of wordlines, the plurality of wordlines including one or more dummy wordlines and one or more normal wordlines; determining whether the first wordline is one of the one or more dummy wordlines by determining, based on the read data, a number of the first memory cells having a first threshold voltage state, the one or more dummy wordlines being wordlines the memory cells of which have been programmed with dummy data, the one or more normal wordlines being wordlines that are not dummy wordlines; and performing a repair algorithm for correcting an error in the read data, selectively according to a result of the determination.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong-Kil Jung, Dae-Seok Byeon
  • Resistive memory device and method of operating the same to reduce leakage current
    Patent number: 9361974
    Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 7, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Dae-Seok Byeon, Yeong-Taek Lee, Chi-Weon Yoon, Hyun-Kook Park, Hyo-Jin Kwon
  • Resistive memory device and operating method
    Patent number: 9355721
    Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chi-Weon Yoon, Hyun-Kook Park, Dae-Seok Byeon
  • CROSS-POINT MEMORY DEVICE INCLUDING MULTI-LEVEL CELLS AND OPERATING METHOD THEREOF
    Publication number: 20160148678
    Abstract: A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.
    Type: Application
    Filed: July 15, 2015
    Publication date: May 26, 2016
    Inventors: HYUN-KOOK PARK, CHI-WEON YOON, DAE-SEOK BYEON
  • MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20160133323
    Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.
    Type: Application
    Filed: July 6, 2015
    Publication date: May 12, 2016
    Inventors: HYO-JIN KWON, YEONG-TAEK LEE, DAE-SEOK BYEON
  • RESISTIVE MEMORY DEVICE AND OPERATING METHOD
    Publication number: 20160125942
    Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
    Type: Application
    Filed: July 16, 2015
    Publication date: May 5, 2016
    Inventors: CHI-WEON YOON, HYUN-KOOK PARK, DAE-SEOK BYEON
  • RESISTIVE MEMORY DEVICE AND OPERATING METHOD
    Publication number: 20160125939
    Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 5, 2016
    Inventors: HYUN-KOOK PARK, YEONG-TAEK LEE, DAE-SEOK BYEON, BO-GEUN KIM
  • RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE
    Publication number: 20160118114
    Abstract: A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.
    Type: Application
    Filed: June 18, 2015
    Publication date: April 28, 2016
    Inventors: HYO-JIN KWON, YEONG-TAEK LEE, DAE-SEOK BYEON
  • RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD THEREOF
    Publication number: 20160099049
    Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.
    Type: Application
    Filed: July 10, 2015
    Publication date: April 7, 2016
    Inventors: Yong-kyu LEE, Yeong-taek LEE, Dae-seok BYEON, In-gyu BAEK, Man CHANG, Lijie ZHANG, Hyun-kook PARK
  • RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD THEREOF
    Publication number: 20160099052
    Abstract: A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.
    Type: Application
    Filed: May 29, 2015
    Publication date: April 7, 2016
    Inventors: Yong-kyu LEE, Yeong-taek LEE, Dae-seok BYEON, In-gyu BAEK, Man CHANG, Lijie ZHANG
  • RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME TO REDUCE LEAKAGE CURRENT
    Publication number: 20160093376
    Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
    Type: Application
    Filed: April 10, 2015
    Publication date: March 31, 2016
    Inventors: YONG-KYU LEE, DAE-SEOK BYEON, YEONG-TAEK LEE, CHI-WEON YOON, HYUN-KOOK PARK, HYO-JIN KWON
  • MEMORY DEVICE HAVING CROSS POINT ARRAY STRUCTURE, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY DEVICE
    Publication number: 20160055904
    Abstract: In a method of operating a memory device having a cross point array structure, the memory device includes multiple tiles, and each of the tiles includes memory cells of multiple layers. The method includes accessing, in a first tile, multiple memory cells of a first layer disposed in a region where at least one first line and at least one second line cross each other, accessing, in the first tile, multiple memory cells of a second layer disposed in a region where at least one first line and at least one second line cross each other, and accessing, after the memory cells of the multiple layers of the first tile are accessed, multiple memory cells included in a second tile. Related memory devices and memory systems are also discussed.
    Type: Application
    Filed: May 19, 2015
    Publication date: February 25, 2016
    Inventors: Hyun-kook Park, Chi-weon Yoon, Yeong-taek Lee, Dae-seok Byeon
  • Memory device having cross point array structure, memory system, and method of operating memory device
    Patent number: 9269430
    Abstract: In a method of operating a memory device having a cross point array structure, the memory device includes multiple tiles, and each of the tiles includes memory cells of multiple layers. The method includes accessing, in a first tile, multiple memory cells of a first layer disposed in a region where at least one first line and at least one second line cross each other, accessing, in the first tile, multiple memory cells of a second layer disposed in a region where at least one first line and at least one second line cross each other, and accessing, after the memory cells of the multiple layers of the first tile are accessed, multiple memory cells included in a second tile. Related memory devices and memory systems are also discussed.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-kook Park, Chi-weon Yoon, Yeong-taek Lee, Dae-seok Byeon
  • Resistive memory device, resistive memory system, and method of operating resistive memory device
    Patent number: 9269429
    Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: February 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Dae-Seok Byeon, Yeong-Taek Lee, Bo-Geun Kim, Yong-Kyu Lee, Hyo-Jin Kwon
  • RESISTIVE MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20160042811
    Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
    Type: Application
    Filed: June 18, 2015
    Publication date: February 11, 2016
    Inventors: HYO-JIN KWON, DAE-SEOK BYEON, YEONG-TAEK LEE, CHI-WEON YOON, YONG-KYU LEE, HYUN-KOOK PARK
  • MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE
    Publication number: 20160035417
    Abstract: A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
    Type: Application
    Filed: April 28, 2015
    Publication date: February 4, 2016
    Inventors: HYUN-KOOK PARK, YOUNG-HOON OH, DAE-SEOK BYEON, YONG-KYU LEE, HYO-JIN KWON
  • MEMORY DEVICES, MEMORY SYSTEMS, AND RELATED OPERATING METHODS
    Publication number: 20160027485
    Abstract: A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.
    Type: Application
    Filed: April 10, 2015
    Publication date: January 28, 2016
    Inventors: HYUN-KOOK PARK, YEONG-TAEK LEE, DAE-SEOK BYEON, CHI-WEON YOON