Abstract: Provided are an organic electric element and an electronic device comprising the same. According to the present invention, the organic electric element uses a mixture of compounds as a phosphorescent host material which can achieve a high light-emitting efficiency and a low driving voltage and can greatly improve a lifespan in an organic electric element.

Abstract: A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.

Abstract: Provided are an organic electric element and an electronic device thereof comprising a mixture of the compounds of Formula 1 and Formula 2 as a phosphorescent host material, and thereby obtaining high light emission efficiency, low driving voltage, and improved lifetime.

Abstract: A fluid discharging device includes a body member including an entrance configured to receive fluid and a passage line through which the fluid is transferred to a chamber, and a first foreign material removing unit coupled to the body member, and expanding and restoring such that foreign materials accumulated on a surface of the first foreign material removing unit is removed.

Abstract: Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including memory cells, each having any one of an erased state or one of a plurality of programmed states, and a memory controller configured to estimate an optimal read voltage associated with at least one of the erased state or one of the programmed states based on a threshold voltage distribution corresponding to at least one of the programmed states. The memory controller may include a threshold voltage distribution checker configured to check a first threshold voltage distribution corresponding to a first programmed state, among the programmed states, and determine an average threshold voltage of the first threshold voltage distribution, and an optimal read voltage estimator configured to estimate a second optimal read voltage corresponding to a second side of the first threshold voltage distribution.

Abstract: An error correction circuit using a BCH code may include a decoder performing at least one of a first error correction decoding using a first error correction capability or a second error correction decoding using a second error correction capability and an encoder generating a codeword based on a message and a generation matrix corresponding to the first error correction capability and generating an additional parity based on the codeword and one or more rows of a parity check matrix corresponding to the second error correction capability, wherein a syndrome vector generated based on a read vector corresponding to the codeword is used during the first error correction decoding and an additional syndrome generated based on the additional parity is used during the second error correction decoding, and wherein the one or more rows are extended from a parity check matrix corresponding to the first error correction capability.

Abstract: Provided is an organic electric element including an electron blocking layer and a hole transport layer capable of improving the luminous efficiency, stability, and lifetime of the organic electric element, and an electronic device including the same.

Abstract: An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values corresponding to hard decision bits, based on soft decision bit sets corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values. The reliability values correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node. All necessary reliability values are not transmitted to each variable node, instead, compressed reliability values are transmitted to the variable node. The variable node receives and retains the compressed reliability values, restores necessary reliability values, and uses them in a decoding operation.

Abstract: A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

Abstract: A semiconductor memory system includes: a semiconductor memory device for storing a code word; a decoder for decoding stored the code word based on a parity check matrix formed of sub-matrices to generate decoded data; and a channel for coupling the semiconductor memory device to the decoder and providing the decoder with the stored code word, wherein the decoder includes: a variable node selecting device for sequentially selecting sub-matrices sharing the same layer of the parity check matrix and sequentially selecting variable nodes respectively corresponding to columns forming the selected sub-matrices; a variable node updating device for updating the selected variable nodes based on a channel message and check node messages provided to the selected variable nodes; and a check node updating device for updating the check nodes based on variable node messages provided to the check nodes coupled to the selected variable nodes.

Abstract: Provided herein may be an error correction decoder based on an iterative decoding scheme using NB-LDPC codes and a memory system having the same. The error correction decoder may include a symbol generator for assigning an initial symbol to a variable node, a reliability value manager for setting and updating reliability values of candidate symbols of the variable node in current iteration, a flipping function value calculator for calculating a flipping function value by subtracting a function value, related to the updated reliability values of remaining candidate symbols other than a target candidate symbol, from another function value, related to the updated reliability value of the target candidate symbol, in the current iteration, and a symbol corrector for changing the hard decision value to the target candidate symbol when the flipping function value is equal to or greater than a first threshold value in the current iteration.

Abstract: An operation method of a decoder may include: performing a first sub-decoding operation on a target data chunk; performing a second sub-decoding operation on candidate chunks and a chip-kill chunk; performing a third sub-decoding operation to determine a global check node; performing a fourth sub-decoding operation to infer and update local variable nodes of the target data chunk and local variable nodes of a data chunk from the global check node; and repeating the first to fourth sub-decoding operations once by a set number of times based on components of the updated local variable nodes.

Abstract: The organic electric element comprising a compound represented by Formula 1 as material of an emission-auxiliary layer and an electronic device thereof are disclosed, and by comprising the compound represented by Formula 1 in an emission-auxiliary layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time of the organic electric element can be improved.

Abstract: A portable communication device is provided.

Abstract: Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.

Abstract: There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.

Abstract: Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correction encoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword on a column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.

Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.

Abstract: A parity check matrix managing technology generating and modifying parity check matrix for encoding and decoding data to be processed in a communication system, memory system, and the like is disclosed. A parity check matrix managing apparatus may include an input device configured to receive a parity check matrix as a modification target; a matrix modifier configured to modify the parity check matrix by performing at least one of a cyclic shift on unit components of at least one row or column in the parity check matrix and a location change between at least two rows or columns in the parity check matrix to generate a modified parity check matrix; and a controller configured to control the matrix modifier to compare a matrix size of the modified parity check matrix with a set matrix size, so that the matrix size is less than or equal to the set matrix size.