Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including memory cells, each having any one of an erased state or one of a plurality of programmed states, and a memory controller configured to estimate an optimal read voltage associated with at least one of the erased state or one of the programmed states based on a threshold voltage distribution corresponding to at least one of the programmed states. The memory controller may include a threshold voltage distribution checker configured to check a first threshold voltage distribution corresponding to a first programmed state, among the programmed states, and determine an average threshold voltage of the first threshold voltage distribution, and an optimal read voltage estimator configured to estimate a second optimal read voltage corresponding to a second side of the first threshold voltage distribution.

Abstract: A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.

Abstract: A method and a portable communication device are provided.

Abstract: Provided is a silicon-based molten composition including silicon, carbon, and a metal in which a solubility parameter (Csisol) defined by Equation (1) below is less than ?0.37, wherein a SiC single crystal is formed by a solution method: Csisol=A?B+?1??2??Equation (1) in Equation (1) above, A is a first energy (A) of a first evaluation lattice including silicon atoms, a carbon atom, and metal atoms in a silicon crystal lattice including metals and carbons, B is a second energy (B) of a second evaluation lattice including silicon atoms and metal atoms in a silicon crystal lattice including metals, ?1 is a constant of ?5.422, and ?2 is a constant of ?9.097.

Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.

Abstract: A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.

Abstract: A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.

Abstract: A method of controlling a user interface using an input image is provided. The method includes storing operation executing information of each of one or more gesture forms according to each of a plurality of functions, detecting a gesture form from the input image, and identifying the operation executing information mapped on the detected gesture form to execute an operation according to a function which is currently operated.

Abstract: A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.

Abstract: The present invention relates to a silicon-based molten composition for forming a SiC single crystal by a solution method, the composition containing silicon, carbon, and a metal satisfying 0.70?Csisol?1.510 with respect to a solubility parameter (Csisol) defined by the following Equation (1): Csisol=A?B+?1??2??Equation (1) wherein, A is first energy (A) of a first evaluation lattice containing silicon atoms, carbon atoms, and metal atoms, in a silicon crystal lattice containing the metal and the carbon; B is second energy (B) of a second evaluation lattice containing silicon atoms and metal atoms, in a silicon crystal lattice containing the metal; ?1 is ?5.422 as a constant value, and ?2 is ?9.097 as a constant value.

Abstract: A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.

Abstract: A semiconductor memory system includes: a semiconductor memory device for storing a code word; a decoder for decoding stored the code word based on a parity check matrix formed of sub-matrices to generate decoded data; and a channel for coupling the semiconductor memory device to the decoder and providing the decoder with the stored code word, wherein the decoder includes: a variable node selecting device for sequentially selecting sub-matrices sharing the same layer of the parity check matrix and sequentially selecting variable nodes respectively corresponding to columns forming the selected sub-matrices; a variable node updating device for updating the selected variable nodes based on a channel message and check node messages provided to the selected variable nodes; and a check node updating device for updating the check nodes based on variable node messages provided to the check nodes coupled to the selected variable nodes.

Abstract: Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.

Abstract: An apparatus for supplying chemical liquid may include a chemical liquid discharging member, a reservoir, a chemical liquid supplying member and a chemical liquid circulating member. The chemical liquid discharging member may discharge a chemical liquid onto a substrate. The reservoir may store the chemical liquid supplied to the chemical liquid discharging member. The chemical liquid supplying member may supply the chemical liquid stored in the reservoir. The chemical liquid circulating member may circulate the chemical liquid from the chemical liquid discharging member to the reservoir.

Abstract: An error correction circuit includes a decoder including a plurality of check node units and variable node units corresponding to a parity check matrix of low density parity check (LDPC) scheme, and configured to generate decoded data by decoding a codeword; a syndrome check circuit configured to calculate a reference value for the codeword based on the parity check matrix, and generate a decoder operation control signal corresponding to the reference value; and a control circuit configured to control whether to operate each of the plurality of check node units and variable node units of the decoder in response to the decoder operation control signal, wherein the decoder decodes the codeword based on check node units and variable node units which operate according to the control of the control circuit among the plurality of check node units and variable node units.

Abstract: A jig configured to clean a bowl of a spin coater includes a base disposed on a spin chuck of the spin coater, the base being configured to rotate by the spin chuck. The jig further includes a guide member extending in a first direction from an edge portion of the base toward an inner cover of the bowl and configured to guide a lower cleaning agent injected to a lower surface of the base to the inner cover of the bowl. The inner cover of the bowl is configured to receive photoresist from under the spin chuck.

Abstract: A method of controlling a user interface using an input image is provided. The method includes storing operation executing information of each of one or more gesture forms according to each of a plurality of functions, detecting a gesture form from the input image, and identifying the operation executing information mapped on the detected gesture form to execute an operation according to a function which is currently operated.

Abstract: An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the c

Abstract: An operation method of a decoder may include: performing a first sub-decoding operation on a target data chunk; performing a second sub-decoding operation on candidate chunks and a chip-kill chunk; performing a third sub-decoding operation to determine a global check node; performing a fourth sub-decoding operation to infer and update local variable nodes of the target data chunk and local variable nodes of a data chunk from the global check node; and repeating the first to fourth sub-decoding operations once by a set number of times based on components of the updated local variable nodes.

Abstract: An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values respectively corresponding to hard decision bits, based on soft decision bit sets respectively corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values, wherein the reliability values respectively correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node.