Patents by Inventor Daisuke Ikeno

Daisuke Ikeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269825
    Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Wakatsuki, Atsuko Sakata, Daisuke Ikeno
  • Patent number: 9911753
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Tomotaka Ariga
  • Patent number: 9905462
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsuko Sakata, Takeshi Ishizaki, Shinya Okuda, Kei Watanabe, Masayuki Kitamura, Satoshi Wakatsuki, Daisuke Ikeno, Junichi Wada, Hirotaka Ogihara
  • Patent number: 9779978
    Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
  • Patent number: 9780111
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Ishizaki, Junichi Wada, Atsuko Sakata, Kei Watanabe, Masayuki Kitamura, Daisuke Ikeno, Satoshi Wakatsuki, Hirotaka Ogihara, Shinya Okuda
  • Publication number: 20170263621
    Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 14, 2017
    Inventors: Satoshi WAKATSUKI, Atsuko SAKATA, Daisuke IKENO
  • Publication number: 20170207236
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Application
    Filed: September 6, 2016
    Publication date: July 20, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Satoshi WAKATSUKI, Takeshl ISHIZAKI, Daisuke IKENO, Tomotaka ARIGA
  • Publication number: 20170196965
    Abstract: The present invention provides a vaccine containing virus-like particles derived from virus particles having an envelope, in which a lipid-component content of the virus-like particles is reduced relative to a lipid-component content of the virus particles.
    Type: Application
    Filed: July 15, 2015
    Publication date: July 13, 2017
    Applicant: THE CHEMO-SERO-THERAPEUTIC RESEARCH INSTITUTE
    Inventors: Kazuhiko KIMACHI, Motoharu ABE, Kazuyuki IKEDA, Hiroto ONUMA, Yukari TSURUDOME, Daisuke IKENO, Kiyoto NISHIYAMA, Tatsufumi ONCHI, Yusuke OOYAMA, Issay ASANO, Ryoichi KITANO
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Publication number: 20170053869
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Application
    Filed: December 31, 2015
    Publication date: February 23, 2017
    Inventors: Atsuko SAKATA, Takeshi ISHIZAKI, Shinya OKUDA, Kei WATANABE, Masayuki KITAMURA, Satoshi WAKATSUKI, Daisuke IKENO, Junichi WADA, Hirotaka OGIHARA
  • Patent number: 9570464
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal nitride film on a side surface of a hole extending in a stacking direction in a stacked body. The method includes forming a second metal nitride film on upper and lower surfaces of second layers and a side surface of the first metal nitride film. The method includes forming metal layers in first air gaps inside the second metal nitride film. The method includes removing the second layers and forming second air gaps between the metal layers. The method includes removing the first metal nitride film exposed to the second air gaps and dividing the first metal nitride film in the stacking direction.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Wakatsuki, Atsuko Sakata, Masayuki Kitamura, Daisuke Ikeno, Takeshi Ishizaki, Tomotaka Ariga
  • Publication number: 20160300845
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
    Type: Application
    Filed: August 18, 2015
    Publication date: October 13, 2016
    Inventors: Takeshi ISHIZAKI, Junichi WADA, Atsuko SAKATA, Kei WATANABE, Masayuki KITAMURA, Daisuke IKENO, Satoshi WAKATSUKl, Hirotaka OGIHARA, Shinya OKUDA
  • Publication number: 20160276204
    Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.
    Type: Application
    Filed: June 26, 2015
    Publication date: September 22, 2016
    Inventors: Atsuko SAKATA, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
  • Publication number: 20160268283
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers; a first electrode layer included in the plurality of electrode layers; a second electrode layer included in the plurality of electrode layers; a first insulating layer provided between the first electrode layer and the second electrode layer, and provided in contact with the first electrode layer and the second electrode layer; a semiconductor portion; a charge storage film; a first conductive film; and second conductive film. The first conductive film is provided between the first electrode layer and the charge storage film, and provided in contact with the first insulating layer. The second conductive film is provided between the second electrode layer and the charge storage film, and provided in contact with the first insulating layer.
    Type: Application
    Filed: July 9, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KITAMURA, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Junichi Wada, Kei Watanabe, Shinya Okuda, Hirotaka Ogihara, Hiroshi Nakazawa, Tomonori Aoyama, Kenji Aoyama, Hideaki Aochi
  • Patent number: 9406694
    Abstract: According to one embodiment, a semiconductor device includes a metal layer containing boron, a semiconductor film extending in a direction intersecting with a direction in which the metal layer extends, a charge storage film provided between the semiconductor film and the metal layer, a first dielectric film provided between the charge storage film and the metal layer, and a nitride film provided between the first dielectric film and the metal layer. The nitride film includes a first titanium nitride film provided in contact with the first dielectric film, a second titanium nitride film provided in contact with the metal layer, and an amorphous nitride film provided between the first titanium nitride film and the second titanium nitride film.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Ikeno, Masayuki Kitamura, Atsuko Sakata
  • Publication number: 20160071942
    Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a first insulating layer, a first floating gate, a second insulating layer, a second floating gate, a third insulating layer, and a control gate. The first insulating layer is provided on the semiconductor substrate. The first floating gate is provided on the first insulating layer. The first floating gate includes silicon. The second insulating layer is provided on the first floating gate. The second floating gate is provided on the second insulating layer. The second floating gate includes ruthenium suicide containing not less than 50 atm % Ru. The third insulating layer is provided on the second floating gate. The control gate is provided on the third insulating layer.
    Type: Application
    Filed: February 27, 2015
    Publication date: March 10, 2016
    Inventors: Daisuke IKENO, Atsuko SAKATA
  • Publication number: 20160064405
    Abstract: According to one embodiment, forming a metal film on an underlying layer, and depositing an oxide film on the metal film using plasma of a mixed gas induced above the metal film. The mixed gas includes a gaseous material source, a gaseous oxidant, and a gaseous reductant.
    Type: Application
    Filed: January 30, 2015
    Publication date: March 3, 2016
    Inventors: SHINYA OKUDA, KEI WATANABE, HIROTAKA OGIHARA, MASAYUKI KITAMURA, TAKESHI ISHIZAKI, DAISUKE IKENO, SATOSHI WAKATSUKI, ATSUKO SAKATA, JUNICHI WADA
  • Patent number: 9231192
    Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: January 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Patent number: 9196823
    Abstract: A magnetoresistive effect element includes the following structure. A first ferromagnetic layer has a variable magnetization direction. A second ferromagnetic layer has an invariable magnetization direction. A tunnel barrier layer is formed between the first and second ferromagnetic layers. An energy barrier between the first ferromagnetic layer and the tunnel barrier layer is higher than an energy barrier between the second ferromagnetic layer and the tunnel barrier layer. The second ferromagnetic layer contains a main component and an additive element. The main component contains at least one of Fe, Co, and Ni. The additive element contains at least one of Mg, Al, Ca, Sc, Ti, V, Mn, Zn, As, Sr, Y, Zr, Nb, Cd, In, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, and W.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Nagamine, Daisuke Ikeno, Koji Ueda, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Patent number: 9178137
    Abstract: A magnetoresistive element includes first and magnetic layers, first and second non-magnetic layers and a W layer. Each of the first and second magnetic layers includes an axis of easy magnetization in a direction perpendicular to a film plane. The first magnetic layer has a variable magnetization direction. The second magnetic layer has an invariable magnetization direction. The first non-magnetic layer is provided between the first and second magnetic layers. The second non-magnetic layer is arranged on a surface of the first magnetic layer opposite to a surface on which the first non-magnetic layer is arranged and contains MgO. The W layer is arranged on a surface of the second non-magnetic layer opposite to a surface on which the first magnetic layer is arranged, and is in contact with the surface of the second non-magnetic layer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: November 3, 2015
    Inventors: Youngmin Eeh, Katsuya Nishiyama, Daisuke Ikeno, Toshihiko Nagase, Tadashi Kai, Daisuke Watanabe