Abstract: An electric connector to be mounted on a printed circuit board, includes a housing having an inner space into which a second electric connector is inserted in a direction in which a plane of the printed circuit board is extensive, and at least one fixer through which the housing is fixed on the printed circuit board, the fixer including an extending portion extending from a floor portion of the housing towards outside of the housing, and making contact at a lower surface thereof with a surface of the printed circuit board, the extending portion being fixed at a lower surface thereof on the surface of the printed circuit board to cause the electric connector to be fixed on the surface of the printed circuit board.

Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer including a first region, a second region and the third region provided between the first region and the second region. The oxide semiconductor layer contains indium (In), gallium (Ga), and zinc (Zn). The first and second regions have thinner film thickness and lower indium (In) concentration than the third region. An insulating film is provided on the third region, and an electrode is provided on the insulating film. A first conductive layer is provided under the first region and electrically connected with the first region. A second conductive layer is provided under the second region and electrically connected with the second region.

Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.

Abstract: According to one embodiment, a resistance change device includes a first electrode including a metal, a second electrode, and an amorphous oxide layer including Si and O between the first and second electrode, the layer having a concentration gradient of O and a first peak thereof in a direction from the first electrode to the second electrode.

Abstract: The electric connector including a housing formed with a plurality of holes into each of which a terminal is inserted, the holes being aligned in a line in a first direction, a rear holder connected to the housing through a hinge such that the rear holder is rotatable relative to the housing, a first engagement unit for connecting the rear holder and the housing to each other, the first engagement unit being arranged at at least one of opposite ends in the first direction, and a second engagement unit for preventing the rear holder and the housing from separating from each other after the rear holder and the housing are connected to each other, the second engagement unit being situated between the holes located adjacent to each other.

Abstract: An electric connector includes a first connector including a first housing in which an inner space is formed, and a second connector including a second housing insertable into the inner space, the first housing including in the inner space a lock engagement portion, the second housing including a lock arm having a lock projection to be engaged with the lock engagement portion, the first housing including in the inner space at least one rib extending in a first direction in which the second housing is inserted into the inner space, the lock arm being formed with a guide space into which the rib is able to be inserted when the second housing is inserted into the inner space.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a TaN layer provided on the first insulating layer and containing tantalum and nitrogen, a TaSiN layer provided on the TaN layer in contact with the TaN layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the TaSiN layer in contact with the TaSiN layer and containing oxygen, and a control electrode provided on the second insulating layer.

Abstract: A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and memory cells at intersections of the first and second wiring lines, the memory cells being stacked perpendicularly to a substrate, each memory cell comprising a variable resistance element; a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines; a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines; and a peripheral circuit layer on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells. The first select transistor layer is provided below the memory cell array perpendicularly to the substrate. The second select transistor layer is provided above the memory cell array perpendicularly to the substrate.

Abstract: A semiconductor memory device comprises: first lines; second lines; memory cells; a first and second select gate transistor; and a control circuit. The first lines are arranged with a certain pitch in a first direction perpendicular to a substrate and are extending in a second direction parallel to the substrate. The second lines are arranged with a certain pitch in the second direction, are extending in the first direction, and intersect the plurality of first lines. The memory cells are disposed at intersections of the first lines and the second lines. The first and second select gate transistors each include a first or second channel line that are connected to a lower end or an upper end of the second line and a first or second gate line. The control circuit controls the first and second select gate transistors independently.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a TaN layer provided on the first insulating layer and containing tantalum and nitrogen, a TaSiN layer provided on the TaN layer in contact with the TaN layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the TaSiN layer in contact with the TaSiN layer and containing oxygen, and a control electrode provided on the second insulating layer.

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.

Abstract: An electric connector to be mounted on a printed circuit board, includes a housing having an inner space into which a second electric connector is inserted in a direction in which a plane of the printed circuit board is extensive, and at least one fixer through which the housing is fixed on the printed circuit board, the fixer including an extending portion extending from a floor portion of the housing towards outside of the housing, and making contact at a lower surface thereof with a surface of the printed circuit board, the extending portion being fixed at a lower surface thereof on the surface of the printed circuit board to cause the electric connector to be fixed on the surface of the printed circuit board.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.

Abstract: A connector terminal includes a pair of terminal contacts sandwiching a male connector therebetween to make electric contact with the male connector, and a terminal body supporting the pair of terminal contacts. The terminal contacts are formed by bending a metal plate having been punched into a designed shape. The terminal contacts each include a contact surface formed by bending a contact part not facing the other contact part and extending towards a central axis of the terminal body.