Patents by Inventor Daisuke Okada

Daisuke Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12598743
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: April 7, 2026
    Assignee: Floadia Corporation
    Inventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 11870188
    Abstract: A coaxial connector set including a first connector to which a coaxial cable having a center conductor and an outer conductor is connected, and a second connector mounted on a circuit board having a ground coupling portion. The first connector has a first outer terminal, and the second connector has a second outer terminal. The first outer terminal has an outer conductor clamp portion, a first outer contact portion, and a tip surrounding portion positioned between the outer conductor clamp portion and the first outer contact portion and surrounding a tip portion of the center conductor. Shortcut coupling paths are formed between the tip surrounding portion and the second outer terminal or the ground coupling portion.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Aoi Tanaka, Katsumi Kohnishi, Daisuke Okada
  • Patent number: 11527075
    Abstract: According to an aspect of the present invention, an information processing apparatus includes an object region detecting unit, a local region detecting unit, an object specifying unit. The object region detecting unit is configured to detect an object region based on one of distance information and luminance information. The local region detecting unit is configured to, when a divided area obtained by dividing the detected object region meets a predetermined condition, detect the divided area as a local region. The object specifying unit is configured to specify, as a specification target object, the object region in which the local region is continuously detected.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 13, 2022
    Assignee: RICOH COMPANY, LTD.
    Inventors: Sadao Takahashi, Daisuke Okada, Sukehiro Kimura, Tabito Suzuki, Yohichiroh Ohbayashi, Hiroki Kubozono, Jun Yoshida
  • Patent number: 11223170
    Abstract: A surface mount connector in which an internal terminal does not extend to a location outside an external terminal is provided. A surface mount connector includes an external terminal that includes a tubular portion that extends in a first direction, an internal terminal that is separated from the external terminal inside the tubular portion when viewed in the first direction, and an insulator that is disposed between the internal terminal and the external terminal and that has a first main surface and a second main surface opposite the first main surface. The insulator inside the tubular portion has a through-hole that extends from the first main surface to the second main surface.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 11, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Aoi Tanaka, Daisuke Okada
  • Publication number: 20210320464
    Abstract: A coaxial connector set including a first connector to which a coaxial cable having a center conductor and an outer conductor is connected, and a second connector mounted on a circuit board having a ground coupling portion. The first connector has a first outer terminal, and the second connector has a second outer terminal. The first outer terminal has an outer conductor clamp portion, a first outer contact portion, and a tip surrounding portion positioned between the outer conductor clamp portion and the first outer contact portion and surrounding a tip portion of the center conductor. Shortcut coupling paths are formed between the tip surrounding portion and the second outer terminal or the ground coupling portion.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Aoi TANAKA, Katsumi KOHNISHI, Daisuke OKADA
  • Patent number: 11108173
    Abstract: A coaxial connector includes internal and external terminals, and an insulation member disposed between the terminals. The external terminal includes a holding portion that holds coaxial cables, and crimping portions. A crimping portion outermost in an arrangement direction of the cables is formed from a plate member bent to follow an outer circumference of the cable, and includes a connection portion connectable with the holding portion between both end portions in the arrangement direction. An inner hook extends inward in the arrangement direction from a point of intersection between the connection portion connectable with the holding portion and a virtual straight line orthogonal to the arrangement direction and passing a center of the cable, in a cross-sectional view orthogonal to a longitudinal direction of the cable. An outer hook extends outward in the arrangement direction from the point of intersection. The inner hook is shorter than the outer hook.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Daisuke Okada
  • Publication number: 20210257376
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Application
    Filed: April 16, 2021
    Publication date: August 19, 2021
    Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
  • Patent number: 11030761
    Abstract: An information processing device includes an image analyzing unit. The image analyzing unit includes an object region setting unit configured to set an object region, for image information obtained by capturing an imaging range, the object region corresponding to an object existing in the imaging range; a luminance information acquiring unit configured to acquire luminance information indicating luminance in the imaging range; and a correcting unit configured to correct the object region based on the luminance information in a luminance detection region set in a lower part of the object region.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 8, 2021
    Assignee: Ricoh Company, Ltd.
    Inventors: Yuu Yamada, Jun Yoshida, Yohichiroh Ohbayashi, Hiroki Kubozono, Daisuke Okada, Shintaroh Kida, Sukehiro Kimura, Tabito Suzuki
  • Patent number: 11011530
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 18, 2021
    Assignee: FLOADIA CORPORATION
    Inventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 10985515
    Abstract: A surface mount connector in which an internal terminal does not extend to a location outside an external terminal is provided. A surface mount connector includes an external terminal that includes a tubular portion that extends in a first direction, an internal terminal that is separated from the external terminal inside the tubular portion when viewed in the first direction, and an insulator that is disposed between the internal terminal and the external terminal and that has a first main surface and a second main surface opposite the first main surface. The insulator inside the tubular portion has a through-hole that extends from the first main surface to the second main surface.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: April 20, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Aoi Tanaka, Daisuke Okada
  • Patent number: 10910394
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 2, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
  • Publication number: 20210021090
    Abstract: A surface mount connector in which an internal terminal does not extend to a location outside an external terminal is provided. A surface mount connector includes an external terminal that includes a tubular portion that extends in a first direction, an internal terminal that is separated from the external terminal inside the tubular portion when viewed in the first direction, and an insulator that is disposed between the internal terminal and the external terminal and that has a first main surface and a second main surface opposite the first main surface. The insulator inside the tubular portion has a through-hole that extends from the first main surface to the second main surface.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Aoi TANAKA, Daisuke OKADA
  • Publication number: 20200381878
    Abstract: A surface mount connector in which an internal terminal does not extend to a location outside an external terminal is provided. A surface mount connector includes an external terminal that includes a tubular portion that extends in a first direction, an internal terminal that is separated from the external terminal inside the tubular portion when viewed in the first direction, and an insulator that is disposed between the internal terminal and the external terminal and that has a first main surface and a second main surface opposite the first main surface. The insulator inside the tubular portion has a through-hole that extends from the first main surface to the second main surface.
    Type: Application
    Filed: August 14, 2020
    Publication date: December 3, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Aoi TANAKA, Daisuke OKADA
  • Publication number: 20200357807
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 12, 2020
    Inventors: Tsutomu OKAZAKI, Akira KATO, Kan YASUI, Kyoya NITTA, Digh HISAMOTO, Yasushi ISHII, Daisuke OKADA, Toshihiro TANAKA, Toshikazu MATSUI
  • Patent number: 10741983
    Abstract: An L-shaped coaxial connector having a coaxial cable includes a coaxial cable including a central conductor portion and an external conductor portion disposed around the central conductor portion and a center conductor portion, an internal terminal connected to the central conductor portion, an external terminal connected to the external conductor portion, and an insulating member disposed between the internal and external terminals. The external terminal includes a cylindrical portion surrounding the first terminal portion and extending in a cylindrical shape in a direction intersecting an axial direction of the coaxial cable. The internal terminal includes a male type first terminal portion having a cylindrical shape and extending in the direction intersecting the axial direction, and a second terminal portion extending to connect from the first terminal portion to the central conductor portion.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yukihiro Kitaichi, Aoi Tanaka, Kenichi Takada, Fumio Mizuki, Kazuo Shima, Daisuke Okada
  • Publication number: 20200203861
    Abstract: A coaxial connector includes internal and external terminals, and an insulation member disposed between the terminals. The external terminal includes a holding portion that holds coaxial cables, and crimping portions. A crimping portion outermost in an arrangement direction of the cables is formed from a plate member bent to follow an outer circumference of the cable, and includes a connection portion connectable with the holding portion between both end portions in the arrangement direction. An inner hook extends inward in the arrangement direction from a point of intersection between the connection portion connectable with the holding portion and a virtual straight line orthogonal to the arrangement direction and passing a center of the cable, in a cross-sectional view orthogonal to a longitudinal direction of the cable. An outer hook extends outward in the arrangement direction from the point of intersection. The inner hook is shorter than the outer hook.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Daisuke OKADA
  • Patent number: 10692878
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 23, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
  • Publication number: 20200161731
    Abstract: A coaxial cable includes a center conductor layer; an insulator layer covering a periphery of the center conductor layer; an outer conductor layer covering a periphery of the insulator layer; a separator layer covering a periphery of the outer conductor layer; a radio wave absorbing resin layer covering a periphery of the separator layer; and an outer sheath covering a periphery of the radio wave absorbing resin layer. The radio wave absorbing resin layer is formed of a material in which a magnetic body is mixed into a resin, and the separator layer is formed by winding a tape-shaped member around the periphery of the outer conductor layer so as to overlap without a gap.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshihiro HIMI, Daisuke OKADA
  • Patent number: 10651611
    Abstract: An L-type coaxial connector is connected to a coaxial cable including a central conductor and an external conductor, and includes a housing, a bushing, and a socket. The housing includes a housing main body, a back-side section, and a crimp section. The housing main body has a first cut section. The back-side section includes a lid section and an extending section extending from the lid section and above which the external conductor is placed. The crimp section extends from the extending section, and its leading end section is bent so as to be opposed to the extending section such that the coaxial cable is interposed therebetween. The extending section has a second cut section, and a joining member joining the external conductor and the extending section is present inside the second cut section.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 12, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Daisuke Okada, Yoshihiro Himi, Katsumi Kohnishi
  • Patent number: 10615168
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 7, 2020
    Assignee: FLOADIA CORPORATION
    Inventors: Shoji Yoshida, Fukuo Owada, Daisuke Okada, Yasuhiko Kawashima, Shinji Yoshida, Kazumasa Yanagisawa, Yasuhiro Taniguchi