Patents by Inventor Daisuke Okada

Daisuke Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150339548
    Abstract: A processing function proposing apparatus includes a status detector that detects a current status of a resource, a request acquisition unit that acquires a composite function requested to be executed from multiple composite functions, each composite function combining multiple unit functions, a function selecting unit to select at least one unit function combined that executes the requested composite function based on the current status of the resource, and a proposing unit that proposes the unit function selected by the function selecting unit.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 26, 2015
    Inventors: Akiko KITAYAMA, Yasuyuki Igarashi, Daisuke Masui, Daisuke Okada, Yuka Saito, Yuto Shibata, Hiroya Uruta, Naoya Tamura, Noboru Tamura, Kazuki Sasayama, Masashi Taniguchi, Chan Gu
  • Patent number: 9196363
    Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Yamakoshi, Daisuke Okada
  • Patent number: 9164705
    Abstract: An image forming apparatus includes an accumulating unit to accumulate documents, a document selecting unit to receive selection of the accumulated documents to be printed, a screen displaying unit to display on a display unit a printing condition setting screen including default values for selecting plural of the accumulated documents and a list of setting items when the selection received by the document selecting unit indicates plural of the accumulated documents, a reset receiving unit to receive selection of the setting item to be changed and resetting of a default value of the selected setting item, a reset control unit to change a content of the setting item into a resetting content when the setting item is resettable or allow the content to remain unchanged when the setting item is not resettable, and a printing unit to print the accumulated document, the setting item of which is reset.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 20, 2015
    Assignee: Ricoh Company, LTD.
    Inventors: Hajime Kubota, Daisuke Okada, Hideaki Matsui, Yuto Shibata
  • Publication number: 20150270279
    Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.
    Type: Application
    Filed: March 20, 2015
    Publication date: September 24, 2015
    Inventors: Tsuyoshi ARIGANE, Digh HISAMOTO, Daisuke OKADA
  • Patent number: 9117849
    Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 25, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
  • Publication number: 20150187782
    Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.
    Type: Application
    Filed: December 29, 2014
    Publication date: July 2, 2015
    Inventors: Hideaki Yamakoshi, Daisuke Okada
  • Publication number: 20150145023
    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Publication number: 20150137215
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
  • Patent number: 8963226
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
  • Publication number: 20140322874
    Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
  • Patent number: 8869946
    Abstract: An emergency stop device for elevators which actuates when an abnormal speed in both ascending and descending directions of a car is detected by one governor. The emergency stop device includes an endless governor rope to perform circulation movement in synchronization with ascent and descent of the car, a governor in an upper part of the shaft that restrains circulation movement of the governor rope when the abnormal speed is detected via the governor rope, an emergency stop device body in the car that brakes the car when the abnormal speed is detected, a swinging body swingably provided in the emergency stop device body, connected to the governor rope, that rotates when the circulation movement of the governor rope is restrained, thereby causing the emergency stop device body to actuate, and a swinging body rotation mechanism which rotates the swinging body in a prescribed direction when the governor rope between the car and the governor has become slack.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 28, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Okada
  • Patent number: 8860997
    Abstract: A preview image of image data to be output is generated, in response to a request from an operation device, and can be displayed via the operation device. A first preview image of the image data is generated based on an output setting for outputting the image data. The first preview image is stored in a storage device. The output setting can be changed based on a changing request from the operation device. It is determined, in response to a second preview request from the operation device, after sending the first preview image, whether the first preview image is to be regenerated, based on the changed output setting. The first preview image stored in the storage device can be sent when the first preview image is not to be regenerated, for example, when a second preview image is not to be generated.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Keisuke Iwasa, Hajime Kubota, Hideaki Matsui, Daisuke Okada, Yuto Shibata
  • Patent number: 8796756
    Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasafumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
  • Publication number: 20140140133
    Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
  • Patent number: 8681360
    Abstract: An image forming apparatus includes a storage unit that stores therein print data and first converted data obtained by reflecting a first print condition in the print data and converting the print data into a printable form; an input receiving unit that receives an input of a reprint instruction to reprint the first converted data; an acquiring unit that acquires a second print condition for reprinting the first converted data; a determining unit that determines whether the first converted data is printable in the second print condition by comparing the acquired second print condition against the first print condition; a converting unit that converts, when it is determined that the first converted data is unprintable in the second print condition, the print data into second converted data by reflecting the second print condition in the print data; a print control unit prints out the second converted data.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: March 25, 2014
    Assignee: Ricoh Company, Limited
    Inventors: Yuka Saito, Daisuke Okada, Nobuhiro Shindo, Hideaki Matsui, Naohiko Kubo, Nobuyuki Iwata, Masahiro Hayashi
  • Patent number: 8643854
    Abstract: An image forming apparatus, connected to an information processing device via a network, includes a receiving section, a memory, an interpretation section, and a transmission section. The receiving section receives a plurality of pieces of print data from the information processing device via the network. The plurality of pieces of print data include first print data for normal printing, second print data for interruption printing, and third print data. The memory has first to third buffers. The first and second buffers store the first and second print data, respectively. The third buffer stores the third print data during execution of the interruption printing of the second print data. The interpretation section interprets the plurality of pieces of print data. The transmission section transmits a reply message to the information processing device in accordance with a result of the third print data interpreted by the interpretation section.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: February 4, 2014
    Assignee: Ricoh Company, Limited
    Inventors: Kazuma Saito, Takeshi Fujita, Hideaki Matsui, Daisuke Okada
  • Publication number: 20140008716
    Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 9, 2014
    Inventors: Tsuyoshi Arigane, Digh Hisamoto, Yutaka Okuyama, Takashi Hashimoto, Daisuke Okada
  • Publication number: 20130334592
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
  • Patent number: 8582161
    Abstract: An image forming apparatus includes a receiving unit; a data saving unit; a drawing data generating unit; a log storage unit that stores a processing log; an image forming unit; and a data management unit. The data management unit, when the print job is analyzed as a time designated print job; causes the data generating unit to generate the drawing data; causes the data saving unit to save the drawing data; that, when analyzed printing being enabled at the designated print time, causes the image forming unit to perform image formation based on the drawing data and causes the log storage unit to store therein a processing log; and that, when printing is analyzed as disabled at the designated print time, performs processing corresponding to a print disabled state preset and causes the log storage unit to store therein a processing log about the processing.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: November 12, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Daisuke Okada, Noboru Tamura, Nobuhiro Shindo, Hideaki Matsui, Hajime Kubota, Yuto Shibata, Takeo Momose, Masahiro Hayashi
  • Patent number: 8570583
    Abstract: An image processing apparatus, method, and computer readable storage medium in which a controller or control means recognizes whether information read from a detachable recording medium can be applied to the image forming apparatus based on the information stored in a memory of the image processing apparatus and a removable recording medium. When the detachable recording medium is recognized as containing information which can be applied to the image processing apparatus, the information from the detachable recording medium is loaded into the image forming apparatus.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: October 29, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Daisuke Okada, Nobuhiro Shindo, Naruhiko Ogasawara, Takeshi Fujita, Kazuma Saito