Patents by Inventor Daisuke Sakurai

Daisuke Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150242106
    Abstract: Methods, systems, and computer-readable media for providing navigation in a hierarchical data set are presented. In some embodiments, a computing device may generate a user interface including a first node as a focused node at a fixed focal point along with a subset of a first plurality of related nodes having a relationship with the first node. In some instances discussed herein, user input may be received selecting a second node as the focused node, such as a scrolling action dragging the second node to the fixed focal point. The user interface may be updated to display a subset of a second plurality of related nodes having a relationship with the second node. In some arrangements, the hierarchical data set may correspond to an organizational chart, a workflow, a directory structure, a categorized list, a taxonomy, or any other type of hierarchical data.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: Citrix Systems, Inc.
    Inventors: Priscila K. PENHA, Kelly May NASH, Daisuke SAKURAI, Shih-Hao YEH
  • Patent number: 9027822
    Abstract: An adhesive layer forming step of forming an adhesive layer on a surface of a substrate; a solder layer forming step of forming a solder layer on the adhesive layer by loading plural solder powders with in-between spaces; and a filler supplying step of supplying fillers to the in-between spaces of the solder powders that have been formed on the adhesive layer are included.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 12, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Daisuke Sakurai
  • Publication number: 20150113446
    Abstract: Methods, systems, and computer-readable media for providing enhanced application interoperability are presented. In some embodiments, a computing device may present, on at least one display screen, a first user interface that is associated with a first application. In response to determining that the at least one display screen has been rotated from a first orientation to a second orientation, the computing device may present, on the at least one display screen, a second user interface that is associated with a second application different from the first application. In one or more embodiments, the second user interface may include at least some information that is contextually related to information included in the first user interface. In addition, a state of the first application may be preserved when the second user interface that is associated with the second application is presented.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 23, 2015
    Inventors: Priscila K. Penha, Kelly M. Nash, Daisuke Sakurai, Shih-Hao Yeh
  • Publication number: 20150113436
    Abstract: Methods, systems, and computer-readable media for providing enhanced message management user interfaces are presented. In some embodiments, a computing device may present a user interface comprising a scrollable content display region that includes at least two message cards and at least two target zones. The computing device may receive first input moving a first message card to a first target zone. In response to receiving the first input, the computing device may perform a first action on a first email message corresponding to the first message card. Thereafter, the computing device may receive second input moving a second message card to a second target zone. In response to receiving the second input, the computing device may perform a second action different from the first action on a second email message corresponding to the second message card. At least one action may be defined by a user of the computing device.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 23, 2015
    Inventors: Priscila K. Penha, Kelly M. Nash, Daisuke Sakurai, Shih-Hao Yeh
  • Patent number: 8921708
    Abstract: An electronic-component mounted body of the present invention includes an electronic component mounted on a circuit board. The electronic component includes multiple component-side electrode terminals, and the circuit board includes multiple circuit-board side electrode terminals for the component-side electrode terminals. The electronic-component mounted body further includes: multiple protruded electrodes formed respectively on the component-side electrode terminals of the electronic component to electrically connect the electronic component and the circuit board; and a dummy electrode formed on the electronic component and electrically connected to the component-side electrode terminal in a predetermined position out of the component-side electrode terminals. The protruded electrode on the component-side electrode terminal in the predetermined position is higher than the protruded electrode on the component-side electrode terminal in a different position from the predetermined position.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Kazuya Usirokawa
  • Patent number: 8922011
    Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Takatoshi Osumi, Daisuke Sakurai
  • Publication number: 20140299986
    Abstract: A plurality of protruding electrodes of a semiconductor chip are in contact with a plurality of electrodes formed on a semiconductor substrate, via a plurality of solder sections. In this state, the solder sections are melted so as to form a plurality of solder bonding sections joined to the protruding electrodes of the semiconductor chip and the electrodes of the semiconductor substrate. Moreover, a distance between a part of the semiconductor chip and the semiconductor substrate is larger than a distance between the other part of the semiconductor chip and the semiconductor substrate, extending at least some of the solder bonding sections. Thus, the solder bonding sections vary in height. Holes are then formed at least in a solder bonding section having a maximum height out of the solder bonding sections. After that, the solder bonding sections are solidified.
    Type: Application
    Filed: November 16, 2012
    Publication date: October 9, 2014
    Inventors: Daisuke Sakurai, Kazuya Usirokawa
  • Patent number: 8809693
    Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: August 19, 2014
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Publication number: 20140217595
    Abstract: In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board with higher connection reliability. A junction that connects an electrode terminal (4) of an electronic component (1) and an electrode terminal (5) of a substrate (2) contains an alloy (8) and a metal (9) having a lower modulus of elasticity than the alloy (8). The junction has a cross section structure in which the alloy (8) is surrounded by the metal (9) having the lower modulus of elasticity.
    Type: Application
    Filed: August 8, 2012
    Publication date: August 7, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke Sakurai, Kazuya Usirokawa, Kiyomi Hagihara
  • Patent number: 8742584
    Abstract: An externally connecting electrode is formed above a semiconductor substrate with interlayer insulation films and disposed in the externally connecting electrode. The externally connecting electrode has a pad metal layer whose upper surface is exposed, a first metal layer formed between the pad metal layer and the semiconductor substrate, and at least two first vias which penetrate the interlayer insulation film and electrically connect the pad metal layer to the first metal layer and are formed in the interlayer insulation film. The maximum interval b between the first vias is larger than the width a of the pad metal layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Panasonic Corporation
    Inventor: Daisuke Sakurai
  • Publication number: 20140010991
    Abstract: A solder transfer substrate, including: a base layer; an adhesive layer arranged on the base layer; and plural solder powders arranged on the adhesive layer, wherein in the base layer, which is a porous member, a plurality of holes, which allow at least a peeling-off liquid to pass therethrough, are formed from a side thereof on which the adhesive layer is not arranged to a side thereof on which the adhesive layer is arranged. Particularly, the adhesive layer has a characteristic of expanding with the peeling-off liquid infused.
    Type: Application
    Filed: January 25, 2012
    Publication date: January 9, 2014
    Applicant: Panasonic Corporation
    Inventor: Daisuke Sakurai
  • Publication number: 20130307146
    Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 21, 2013
    Applicant: Panasonic Corporation
    Inventors: Takatoshi OSUMI, Daisuke SAKURAI
  • Patent number: 8575751
    Abstract: A conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize conflicting functions, namely, improvement in adhesion strength with the electrode and reduction of contact resistance.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Publication number: 20130181041
    Abstract: An adhesive layer forming step of forming an adhesive layer on a surface of a substrate; a solder layer forming step of forming a solder layer on the adhesive layer by loading plural solder powders with in-between spaces; and a filler supplying step of supplying fillers to the in-between spaces of the solder powders that have been formed on the adhesive layer are included.
    Type: Application
    Filed: August 25, 2011
    Publication date: July 18, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Daisuke Sakurai
  • Publication number: 20130170165
    Abstract: An electronic-component mounted body of the present invention includes an electronic component mounted on a circuit board. The electronic component includes multiple component-side electrode terminals, and the circuit board includes multiple circuit-board side electrode terminals for the component-side electrode terminals. The electronic-component mounted body further includes: multiple protruded electrodes formed respectively on the component-side electrode terminals of the electronic component to electrically connect the electronic component and the circuit board; and a dummy electrode formed on the electronic component and electrically connected to the component-side electrode terminal in a predetermined position out of the component-side electrode terminals. The protruded electrode on the component-side electrode terminal in the predetermined position is higher than the protruded electrode on the component-side electrode terminal in a different position from the predetermined position.
    Type: Application
    Filed: September 22, 2011
    Publication date: July 4, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke Sakurai, Kazuya Usirokawa
  • Patent number: 8450848
    Abstract: A semiconductor device includes an electronic part including an electrode, a substrate including a substrate electrode electrically connected to the first electrode on an upper surface thereof, the first substrate electrode and the first electrode being arranged, facing each other, a connecting member configured to connect the electrode with the substrate electrode, and a sealing material including a first resin portion which contains flux and contacts at least a connection portion between the connecting member and the substrate electrode, and a second resin portion which contains a lower concentration of flux than that of the first resin portion. A gap between the electronic part and the substrate is filled with the sealing film.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: May 28, 2013
    Assignee: Panasonic Corporation
    Inventor: Daisuke Sakurai
  • Patent number: 8367539
    Abstract: The semiconductor device manufacturing method includes the steps of attaching two or more solder particles on at least one electrode among a plurality of electrodes of an electronic component, arranging the electrode of the electronic component and an electrode of a circuit board so as to oppose each other, abutting the solder particles attached on a surface of the electrode of the electronic component to the electrode of the circuit board and heating the solder particles, and connecting electrically the electrode of the electronic component and the electrode of the circuit board via two or more solder joint bodies made by melting the solder particles.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventor: Daisuke Sakurai
  • Publication number: 20120295939
    Abstract: A method of suppressing the proliferation of virus comprises administering an antiviral agent comprising as an effective component at least one member selected from the group consisting of 5,7,4?-trihydroxy-3?,5?-dimethoxyflavone, 3-hydroxypyridine, p-hydroxybenzaldehyde and vanillin to one in need of suppressing of viral proliferation.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Inventors: Yuuzou TSUCHIDA, Kunitomo WATANABE, Mamoru KOKETSU, Tsugiya MURAYAMA, Kotarou TSUCHIDA, Daisuke SAKURAI, Mitsuo KAWABE
  • Publication number: 20120168961
    Abstract: An externally connecting electrode is formed above a semiconductor substrate with interlayer insulation films and disposed in the externally connecting electrode. The externally connecting electrode has a pad metal layer whose upper surface is exposed, a first metal layer formed between the pad metal layer and the semiconductor substrate, and at least two first vias which penetrate the interlayer insulation film and electrically connect the pad metal layer to the first metal layer and are formed in the interlayer insulation film. The maximum interval b between the first vias is larger than the width a of the pad metal layer.
    Type: Application
    Filed: March 8, 2012
    Publication date: July 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventor: DAISUKE SAKURAI
  • Publication number: 20120125676
    Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi