Patents by Inventor Daisuke Shibata

Daisuke Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220382500
    Abstract: An image forming apparatus capable of transmitting paper attribute information set during job interruption. The image forming apparatus, which has an image forming device and a paper feeding part storing paper and is communicable with a management server, holds paper attribute information in association with the paper feeding part, executes an image forming job that causes the image forming device to perform a series of image forming using the paper stored in the paper feeding part, generates an execution log of the image forming job based on the attribute information, and when the attribute information corresponding to the paper feeding part is changed during the execution of the image forming job, generates an execution log including the attribute information before/after the change and transmits the generated execution log to the management server.
    Type: Application
    Filed: April 27, 2022
    Publication date: December 1, 2022
    Inventor: Daisuke Shibata
  • Patent number: 11515412
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 29, 2022
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Shinji Ujita, Daisuke Shibata, Satoshi Tamura
  • Publication number: 20220376055
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.
    Type: Application
    Filed: September 25, 2020
    Publication date: November 24, 2022
    Inventors: Daisuke SHIBATA, Satoshi TAMURA, Naohiro TSURUMI
  • Publication number: 20220363935
    Abstract: The present invention provides a coating liquid comprising a hydroxyl group-containing resin, an inorganic layered compound and a liquid medium, wherein an amount of sodium (Na) in the coating liquid is 2,500 ppm or less on a weight basis relative to a solids content of the coating liquid.
    Type: Application
    Filed: November 11, 2020
    Publication date: November 17, 2022
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hiromi YAMANISHI, Daisuke SHIBATA
  • Publication number: 20220344518
    Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.
    Type: Application
    Filed: August 11, 2020
    Publication date: October 27, 2022
    Inventors: Naohiro TSURUMI, Daisuke SHIBATA, Satoshi TAMURA
  • Patent number: 11481266
    Abstract: A server apparatus collects, from a plurality of information processing apparatuses, time series information indicating a change over time in settings and a state of each information processing apparatus, and error information indicating an error that has occurred in each information processing apparatus, generates learning data including the collected information, and generates a diagnostic model, which is a trained model for a malfunction diagnosis in the information processing apparatus, through learning based on the generated learning data. The information processing apparatus obtains the diagnostic model from the server apparatus, outputs a diagnosis result indicating a likelihood that an error will occur in the information processing apparatus by collecting information necessary for the malfunction diagnosis within the information processing apparatus and executing the malfunction diagnosis using the collected information and the obtained diagnostic model.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 25, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Daisuke Shibata
  • Patent number: 11412763
    Abstract: The problem of the invention is to provide a malt beverage which has rich feeling, a reduced grain smell, and can also be produced at a low cost. The means for solving the problem is a malt beverage containing ?-cadinene at a concentration of 3-10 ppb.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 16, 2022
    Assignees: ASAHI GROUP HOLDINGS, LTD., ASAHI BREWERIES, LTD.
    Inventors: Tamaki Morishita, Shigekuni Noba, Hiroo Yamaguchi, Daisuke Shibata
  • Patent number: 11362206
    Abstract: A nitride semiconductor device includes: a substrate having a first main surface and a second main surface; a first nitride semiconductor layer of a first conductivity type provided above the first main surface; a second nitride semiconductor layer of a second conductivity type provided above the first nitride semiconductor layer; a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer provided above the second nitride semiconductor layer and on an inner surface of the first opening; a gate electrode provided above the electron transport layer and covering the first opening; a source electrode connected to the second nitride semiconductor layer; a drain electrode provided on a second main surface-side of the substrate; and a high-resistance layer provided between the second nitride semiconductor layer and the electron transport layer in the first opening, the high-resistance layer including a nitride semiconductor.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC CORPORATION
    Inventors: Masahiro Ogawa, Daisuke Shibata, Satoshi Tamura
  • Publication number: 20220157980
    Abstract: A field-effect transistor includes a substrate having conductivity and made of gallium nitride, a buffer layer provided on the substrate and made of C-doped GaN, a drift layer provided on the buffer layer and made of undoped GaN, and a channel layer provided on the drift layer, made of undoped AlGaN, and joined to the drift layer by heterojunction. A gate electrode is provided on the channel layer. A source electrode and a drain electrode are each provided in regions on both sides of the gate electrode on the channel layer.
    Type: Application
    Filed: August 5, 2019
    Publication date: May 19, 2022
    Inventors: Shinji UJITA, Satoshi TAMURA, Masahiro OGAWA, Daisuke SHIBATA, Hiroyuki HANDA
  • Publication number: 20220154031
    Abstract: The present invention provides a gas barrier laminate having a laminated structure comprising a barrier layer, an inorganic material layer and a base material in this order, wherein the barrier layer includes a water-soluble resin and a condensate of hydrolyzed metal alkoxide, a ratio of an oxygen transmission rate (B) of the gas barrier laminate measured under conditions of a temperature of 40° C. and a relative humidity of 0% RH to an oxygen transmission rate (A) of the gas barrier laminate measured under conditions of a temperature of 23° C. and a relative humidity of 0% RH is 1.80 or less, and the oxygen transmission rate (B) is 1.00 (cc/(m2·day·atm)) or less.
    Type: Application
    Filed: March 11, 2020
    Publication date: May 19, 2022
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Daisuke SHIBATA, Hiromi YAMANISHI
  • Patent number: 11329175
    Abstract: A semiconductor relay includes: a substrate; a semiconductor layer of a direct transition type which is on the substrate and which has semi-insulating properties; a p-type semiconductor layer on at least part of the semiconductor layer; a first electrode; and a second electrode. The first electrode is electrically connected to the semiconductor layer and in contact with the p-type semiconductor layer. The second electrode is spaced apart from the first electrode and at least partially in contact with one of the semiconductor layer and the substrate, and the first electrode includes a first opening part.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 10, 2022
    Assignee: Panasonic Holdings Corporation
    Inventors: Nanako Hirashita, Satoshi Tamura, Daisuke Shibata, Shinji Ujita
  • Publication number: 20220135827
    Abstract: The present invention provides a gas barrier laminate having a laminated structure comprising a barrier layer, an inorganic material layer and a base material in this order, wherein: the barrier layer includes a water-soluble resin and a condensate of hydrolyzed metal alkoxide; and a frictional force of the barrier layer measured by atomic force microscopy is 3.0×10?4 (V) or less.
    Type: Application
    Filed: February 14, 2020
    Publication date: May 5, 2022
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Daisuke SHIBATA
  • Patent number: 11316215
    Abstract: A battery structure includes a plurality of batteries each made of lithium-ion secondary battery; and a plurality of arrangement portions in which the plurality of batteries are arranged. The plurality of arrangement portions are divided into two groups of: a upper heat transfer group having heat transfer orders higher than a center value of the heat transfer orders, where the heat transfer orders are respective amount of heat transfer from the batteries being ranked in descending order; and a lower heat transfer group having the heat transfer orders lower than the center value. A battery among the plurality of batteries showing the highest value of a lithium deposition tolerance which represents a degree of lithium being unlikely to deposit during charge/discharge operation, is disposed in a high tolerance arrangement portion in the plurality of arrangement portions, the high tolerance arrangement portion belonging to the upper heat transfer group.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 26, 2022
    Assignee: DENSO CORPORATION
    Inventors: Yuta Shimonishi, Shuhei Yoshida, Daisuke Shibata, Hiroyoshi Yamamoto
  • Patent number: 11277536
    Abstract: An image reading apparatus configured to cause a document placed on a document tray to be conveyed based on information about a thickness of the document includes a detector configured to detect the document placed on the document tray, a display device configured to display an object for setting the thickness of the document when the detector detects the document placed on the document tray, a sheet conveyance controller configured to cause a sheet conveyance device to convey the document based on information about the thickness of the document set by the object displayed by the display device, and a reader configured to read an image of the document conveyed by the sheet conveyance device, wherein the image reading apparatus receives a setting as to whether a screen for setting the thickness of the document is to be displayed when the detector detects the placed document.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: March 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Daisuke Shibata
  • Publication number: 20220059660
    Abstract: A nitride semiconductor device includes: a substrate; an n-type drift layer; a p-type blocking layer; a gate opening which penetrates through the blocking layer to the drift layer; an electron transport layer and an electron supply layer provided on an inner face of the gate opening; a gate electrode above the electron supply layer and covering the gate opening; a source opening penetrating through the electron supply layer and the electron transport layer to the blocking layer; a source electrode covering the source opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the blocking layer; and a drain electrode on a side of the substrate opposite from a side on which the blocking layer is located. A bottom face of the gate electrode is closer to the drain electrode than a bottom face of the blocking layer is.
    Type: Application
    Filed: November 25, 2019
    Publication date: February 24, 2022
    Inventors: Daisuke SHIBATA, Satoshi TAMURA, Masahiro OGAWA
  • Publication number: 20210310014
    Abstract: Gene expression is regulated (ON/OFF switching) by regulating the chromatin structure, and a several tens of genes (multigene) set introduced into genetically modified crops is stably expressed by the regulation. A plant recombinant gene expression regulatory platform DNA sequence comprising (1) an artificial alphoid DNA sequence having a hierarchical repetitive structure of an alphoid DNA that forms a centromere of a human chromosome and having a nucleotide sequence a part of which is replaced by a binding site of a gene expression regulator (inducer); and (2) a multigene (a plurality of genes) expression cassette sequence, wherein the artificial alphoid DNA sequence is linked to upstream (5? side) and downstream (3? side) of the cassette sequence; and a method for regulating the expression of a recombinant gene in a plant body using the sequence.
    Type: Application
    Filed: August 5, 2019
    Publication date: October 7, 2021
    Applicant: KAZUSA DNA RESEARCH INSTITUTE
    Inventors: Hiroshi MASUMOTO, Daisuke SHIBATA, Jun-ichirou OHZEKI, Koei OKAZAKI, Kazuto KUGOU, Koichiro OTAKE, Jekson ROBERTLEE
  • Publication number: 20210306489
    Abstract: An information processing apparatus that is capable of managing information about operations preceding start of usage of a function while associating with information about operations performed between the start and end of usage of the function. The information processing apparatus includes an operation panel, a display control unit, and a recording unit. The operation panel has a display function and accepts an operation from a user. The display control unit controls the operation panel so as to display an operation object that causes to execute a predetermined function on a screen of the operation panel. The recording unit records information about events concerning operations performed between start and end of the predetermined function and information about an event preceding the start of the predetermined function into a storage unit while associating them to each other.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 30, 2021
    Inventors: Satoshi Okuma, Daisuke Shibata, Jun Tanaka
  • Publication number: 20210186060
    Abstract: The problem of the invention is to provide a malt beverage which has rich feeling, a reduced grain smell, and can also be produced at a low cost. The means for solving the problem is a malt beverage containing ?-cadinene at a concentration of 3-10 ppb.
    Type: Application
    Filed: January 23, 2018
    Publication date: June 24, 2021
    Applicants: Asahi Group Holdings, Ltd., ASAHI BREWERIES, LTD.
    Inventors: Tamaki MORISHITA, Shigekuni NOBA, Hiroo YAMAGUCHI, Daisuke SHIBATA
  • Publication number: 20210179882
    Abstract: The present invention provides a coating fluid for forming a gas barrier layer, the coating fluid including; a liquid medium containing water; and a resin having at least one type of functional group selected from the group consisting of a hydroxy group, a carboxy group, an amino group, and a sulfo group, in which an average particle size of the resin is 100 to 600 nm.
    Type: Application
    Filed: November 27, 2018
    Publication date: June 17, 2021
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Nobuhiro OOSAKI, Makiko MIURA, Daisuke SHIBATA
  • Publication number: 20210167061
    Abstract: Nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity above the substrate; a second nitride semiconductor layer of a second conductivity different from the first conductivity, above the first nitride semiconductor layer a first opening penetrating through the second nitride semiconductor layer; an electron transport layer and an electron supply layer disposed along inner surfaces of the first opening, in stated sequence from the substrate-side; a gate electrode above the electron supply layer, covering the first opening; a source electrode connected to the electron supply layer and the electron transport layer, at a position separated from the gate electrode; and a drain electrode on a surface of the substrate opposite to a surface on which the first nitride semiconductor layer is disposed. At least part of the second nitride semiconductor layer is fixed to a potential different from a potential of the source electrode.
    Type: Application
    Filed: July 11, 2019
    Publication date: June 3, 2021
    Inventors: Daisuke SHIBATA, Satoshi TAMURA, Masahiro OGAWA