Abstract: A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.

Abstract: A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. The apparatus is adapted to receive a low power mode indication, and includes: a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and a power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.

Abstract: A method for testing an integrated circuit, that includes: (a) providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad, and providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad; (b) comparing between a first test result and a second test result, wherein the first test result represents a state of the first memory element sampled a predefined period after a provision of the first signal and the second test result represents a state of the second memory element sampled a predefined period after a provision of the second signal; (c) altering the predefined period; and (d) repeating the stages of providing, comparing and altering until detecting a time difference between a first path propagation period and a second path propagation period.

Abstract: A method and a device having synchronizing capabilities, the device includes; (i) a first circuit that is adapted to receive a first clock signal; (ii) a second circuit that is adapted to receive a second clock signal; wherein the first and second clock signals and mutually asynchronous; and a (iii) synchronizer that is coupled between the first and second circuit and is adapted to receive the second clock signal, to receive an input signal from the first circuit and to output an output signal of definite values to the second circuit, wherein the input signal is synchronized with the first clock signal and the output signal is synchronized with the second clock signal.

Abstract: A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path.

Abstract: A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points.

Abstract: A system that includes a first flip flop that is serially coupled to a second flip flop. The first flip flop includes a transfer circuit that is coupled between a master latch and a slave latch. The master latch of the first flip flop latches a scan data signal during a first portion of a cycle of a first clock signal that is provided to the first flip flop. The transfer circuit is conductive during a sub-portion of a second portion of the cycle of the first clock signal. The sub-portion starts after an occurrence of a predefined change in a control signal provided to the slave latch. The predefined change occurs after an estimated start of a first portion of a cycle of a second clock signal that is provided to the second flip flop. A master latch of the second flip flop latches the scan data signal during a first portion of a next cycle of the second clock signal.

Abstract: A method for race prevention includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. A device having race prevention capabilities includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and a start point of a second scan mode activation period of the output latching logic.

Abstract: A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.

Abstract: Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor.

Abstract: A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits.

Abstract: Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor.

Abstract: A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities.

Abstract: A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits.

Abstract: A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path.

Abstract: A device having protection capabilities, the device includes a voltage supply unit that is connected to an integrated circuit and provides a supply voltage to the integrated circuit; wherein the integrated circuit includes: a security real time clock generator that includes an input; a masking unit that is connected to the input, wherein the masking unit isolates the input when a voltage supply monitor is disabled; and wherein the voltage supply monitor monitors the voltage supply unit and wherein a change in a level of supply voltage affects a level of a signal provided to the input.

Abstract: A method for evaluating a quiescent current, the method includes: measuring, when a module is at a first mode, a first voltage drop on a first resistor that is coupled between a supply pin of an integrated circuit that comprises the module and a first test pin of the integrated circuit; assessing, when the module is at a second mode, a second voltage drop on a second resistor that is coupled between the supply pin and a second test pin of the integrated circuit; and evaluating a quiescent current of the module in response to the first and second voltage drops; wherein expected values of quiescent current of the module differ from one mode to the other; and wherein a resistance of the first resistor differs from the resistance of the second resistor.

Abstract: A device having a power supply monitoring capabilities, the device includes: a power supply unit; at least one real time clock generator counter adapted to receive a supply voltage from the power supply unit; a fixed value storage circuit that is un-accessible to software executed by a processor; wherein the fixed value storage circuit stores a fixed value; wherein the fixed value includes multiple bits; a volatile storage unit, being accessible to the processor; wherein the volatile storage unit is adapted to: (i) store a reset value after being reset; (ii) receive the fixed value during an initialization state; and (iii) store the fixed value until being reset; wherein the volatile storage unit is designed such that there is a low probability that the reset value equals the fixed value; and a comparator adapted to provide a tamper indication if the fixed value stored at the fixed value storage circuit differs from a value stored at the volatile storage unit.

Abstract: A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique.

Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.