Abstract: Apparatuses and methods to write new data of a first block size are provided. A particular method may include writing old data from a destination block of a second block size of a data drive to a first buffer of the second block size. The old data may be written according to address information of the old data and without overwriting the new data in the first buffer. The method may further include writing zeros to a second buffer of the second block size according to the address information of the old data. The zeros written in the second buffer may correspond with the old data written in the first buffer.

Abstract: A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.

Abstract: A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.

Abstract: A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.

Abstract: At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.

Abstract: At least one standard size data block of a storage device is scanned for a logically bad pattern. If the logically pad pattern is detected, a block address that is associated with the standard size data block is added to a bad block table. If the logically pad pattern is not detected, it may be determined if the block address associated with the standard size data block is in the bad block table. If the logically pad pattern is not detected and if the block address associated with the standard size data block is in the bad block table, the block address may be removed from the bad block table. The logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.

Abstract: A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.

Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.

Abstract: A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.

Abstract: A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.

Abstract: A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

Abstract: A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

Abstract: A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.

Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.

Abstract: A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.

Abstract: A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.

Abstract: A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.

Abstract: Methods and a computer program product related to the management of possibly logically bad blocks in storage devices are disclosed. A logically bad pattern is placed in a standard size data block if data associated with the data block has previously been stored or is waiting to be stored, but has subsequently become lost. The logical block address associated with the data block is stored in a bad block table. The possibly logically bad pattern is able to be detected, and the bad block table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given if the logical block address is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated to fill the standard size data block.

Abstract: If data is lost a possibly logically bad pattern is placed in a standard size data block in a storage device, and the Logical Block Address associated with the data block is inserted in a Bad Block Table. The possibly logically bad pattern is able to be detected, and the Bad Block Table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given to a host if a Logical Block Address associated with the standard size data block is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated the requisite number of instances to fill the standard size data block.

Abstract: Mechanisms for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With these mechanisms, the device driver is responsible for managing queues for communicating requests between applications in a logical partition and the endpoint. The device driver further invokes memory management via device driver services. The device driver services are responsible for managing memory accessible by the endpoint, including the address translation and protection table (ATPT) or a root complex and the address translation caches (ATCs) of the endpoint. The device driver services may associate untranslated addresses for data structures used to communicate between a system image and the endpoint. The endpoint may request translations of the untranslated addresses and may cache the translations in the ATCs.