Abstract: A method, system and computer program product are provided for implementing and processing a block extent granularity authorization mechanism for a Coherent Accelerator Processor Interface (CAPI) adapter. The CAPI adapter generates an authorization table with multiple authorization entries, each authorization entry including an Authorization Handle with CAPI server registers identification (ID) including a start Logical Block Address of the extent and range of Logical Block Addresses for each extent. When a command is received an authentication process uses the Authorization Handle contained in the received command and an Authorization Entry in the Authorization Table indexed by the Authorization Handle to authenticate the received command to prevent unauthorized data access.

Abstract: A method, system and computer program product are provided for implementing and processing a block extent granularity authorization mechanism for a Coherent Accelerator Processor Interface (CAPI) adapter. The CAPI adapter generates an authorization table with multiple authorization entries, each authorization entry including an Authorization Handle with CAPI server registers identification (ID) including a start Logical Block Address of the extent and range of Logical Block Addresses for each extent. When a command is received an authentication process uses the Authorization Handle contained in the received command and an Authorization Entry in the Authorization Table indexed by the Authorization Handle to authenticate the received command to prevent unauthorized data access.

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization command flow processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client builds a command including start LBA and number of LBAs and Child Authorization Handle. The Application Client sends the command directly to the CAPI Adapter via the Application Clients CAPI Server Registers assigned to the specific Application Client. The CAPI adapter validate that the requesting Client is authorized to perform the command using the Authorization Handle and the receiving CAPI Server Register address. The CAPI Adapter executes the validated command and sends completion back to the Application Client.

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization command flow processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client builds a command including start LBA and number of LBAs and Child Authorization Handle. The Application Client sends the command directly to the CAPI Adapter via the Application Clients CAPI Server Registers assigned to the specific Application Client. The CAPI adapter validate that the requesting Client is authorized to perform the command using the Authorization Handle and the receiving CAPI Server Register address. The CAPI Adapter executes the validated command and sends completion back to the Application Client.

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client requests authorization to a File from a system processor file system. The file system validates the request, determines the location of each Extent that comprises the File, and requests authorization to each Extent from a System CAPI Authorization manager. The System CAPI Authorization manager requests the CAPI Client manager to assign a Child Client ID and CAPI Server Register range to the requesting Application Client and requests a previously authorized CAPI Parent Client to authorize the Child ID to the list of Extents. The CAPI Parent Client sends a Create Authorizations command to the CAPI Adapter via the Parent's CAPI Server Registers.

Abstract: Embodiments described herein include a PSL engine that includes various memory elements that permit the engine to grant locks on particular portions of data in a stripe in a RAID storage system. The PSL engine can assign (or lock) different blocks of the stripe for different operations. The PSL engine can grant locks to multiple operations for the same stripe if the operations access mutually exclusive blocks of the stripe. Each time a new operation is requested, the PSL engine determines whether the operation would affect a stripe data block that is currently assigned to another operation. If the new operation corresponds to a block of data in the stripe that includes data locked by another operation, the PSL engine assigns the new operation to a wait list. In one embodiment, the PSL engine maintains a wait list for each of the stripes in the RAID system.

Abstract: A method for performing a cycle update on a RAID storage device by a storage system includes storing first data in a first buffer. The method additionally includes retrieving a command block associated with the first data, and executing the command block to perform a set of operations in a sequence specified by the command block. The set of operations includes reading second data from an address of the RAID storage device and generating redundant data based on the first data with the second data. The set of operations further includes storing the redundant data in a second buffer and writing the first data to the address of the RAID storage device when the RAID storage device is a data storage device, and writhing the redundant data stored in the second buffer to the address of the RAID storage device when the RAID storage device is a parity storage device.

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client requests authorization to a File from a system processor file system. The file system validates the request, determines the location of each Extent that comprises the File, and requests authorization to each Extent from a System CAPI Authorization manager. The System CAPI Authorization manager requests the CAPI Client manager to assign a Child Client ID and CAPI Server Register range to the requesting Application Client and requests a previously authorized CAPI Parent Client to authorize the Child ID to the list of Extents. The CAPI Parent Client sends a Create Authorizations command to the CAPI Adapter via the Parent's CAPI Server Registers.

Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization and deauthorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. The Application Client, such as an Application Child Client sends a Delete Authorizations command to the CAPI Adapter via the Client CAPI Server Registers assigned to the specific Application Client. The CAPI Adapter deletes the Authorizations in all Lists in the Delete Authorizations command.

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs writes to storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs a host read and a cache destage simultaneously from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs cache line updates for writes, reads, and destages from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages cache line updates for purges from storage write cache with no firmware involvement for greatly enhancing performance.