Abstract: There are provided relaxation oscillators and methods for controlling the same. A relaxation oscillator includes a load device, a switching device, a fine-tuning varactor, and a current source. The load device is configured to provide a variable oscillator output based on a variable input reference voltage. The switching device is connected in signal communication with the load device and is configured to become active and inactive based on the variable oscillator output. The fine-tuning varactor is connected in signal communication with the switching device and is configured to provide fine-tuning of the variable oscillator output when the switching device is active. The current source is connected in signal communication with the switching device and is configured to provide coarse-tuning of the variable oscillator output when the switching device is active.

Abstract: A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal III-V semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p.

Abstract: A hybrid circuit includes a current-starved voltage-controlled circuit configured to adjust a first type of signal difference, and a phase-interpolated voltage controlled circuit configured to adjust a second type of signal difference. The current-starved circuit and the phase-interpolated circuit cooperate to provide improved operational performance of the hybrid circuit.

Abstract: Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

Abstract: A passive radio frequency transponder (RF tag) having a diode rectifier receiver circuit outside the tag power rectification circuit, the tag power rectification circuit supplying power to the electronics of the RF tag. An additional innovative low current circuit protect the signal capacitor from overvoltage produced by the signal diode. An innovative circuit also clips the signal and sharpens it. An innovative low current circuit is used as a comparator to sharpen the signal pulses.

Abstract: A passive RF tag is disclosed in which the tag contains a tag oscillator for determining the modulation frequency of modulating the backscatter signal, and the tag oscillator frequency is stabilized when the tag modulates the backscatter signal.

Abstract: Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.

Abstract: A Write Broadcast system and method uses a base station to write sent data to all or some selected number (sub group) of tags in a base station field simultaneously. By unselecting the tags that have been successfully written to, and requesting a response from the remaining tags in the field (or sub group), the system determines, by receiving a response to the request, that there are tags in the field (sub group) that were unsuccessfully written to. Another Write Broadcast signal is sent to these tags. The system is useful for quickly (simultaneously) “stamping” information on the tag memory of a large number of tags in the field of the base station.

Abstract: A passive RF tag is disclosed in which the tag contains a tag oscillator for determining the modulation frequency of modulating the backscatter signal, and the tag oscillator frequency is stabilized when the tag modulates the backscatter signal.

Abstract: A multi-junction solar cell device (10) is provided. The multi-junction solar cell device (10) comprises either two or three active solar cells connected in series in a monolithic structure. The multi-junction device (10) comprises a bottom active cell (20) having a single-crystal silicon substrate base and an emitter layer (23). The multi-junction device (10) further comprises one or two subsequent active cells each having a base layer (32) and an emitter layer (23) with interconnecting tunnel junctions between each active cell. At least one layer that forms each of the top and middle active cells is composed of a single-crystal semiconductor alloy that is substantially lattice-matched to the silicon substrate (22). The polarity of the active p-n junction cells is either p-on-n or n-on-p.

Abstract: A Write Broadcast system and method uses a base station to write sent data to all or some selected number (sub group) of tags in a base station field simultaneously. By unselecting the tags that have been successfully written to, and requesting a response from the remaining tags in the field (or sub group), the system determines, by receiving a response to the request, that there are tags in the field (sub group) that were unsuccessfully written to. Another Write Broadcast signal is sent to these tags. The system is useful for quickly (simultaneously) “stamping” information on the tag memory of a large number of tags in the field of the base station.

Abstract: A phase detector (and method therefor), includes a first flip-flop for sampling an incoming data signal in accordance with a first local clock signal to produce a first sampled data signal, a second flip-flop for sampling the incoming data signal in accordance with a second local clock signal to produce a second sampled data signal, and a third flip-flop for sampling the second sampled data signal, as based on the first sampled data signal, to produce a binary control signal. The third flip-flop comprises a double-edge flip-flop.

Abstract: A passive RF tag is disclosed in which the tag contains a tag oscillator for determining the modulation frequency of modulating the backscatter signal, and the tag oscillator frequency is stabalized when the tag modulates the backscatter signal.

Abstract: An active RF transponder is provided with a wake-up circuit that wakes the RF transponder from a sleep state upon detection of an RF interrogating signal. The active RF transponder includes a battery, an antenna adapted to receive RF signals from an interrogator, and electronic circuitry providing the various RF transponder functions of sending/receiving signals and storing data. A first embodiment of the invention includes a wake-up circuit that periodically checks for the presence of an RF signal at the antenna. The wake-up circuit is coupled to the antenna and includes a switch adapted to selectively couple the battery to the electronic circuitry and provide electrical power thereto upon detection of the RF signals by the antenna. The wake-up circuit further comprises an oscillator providing a clock signal having a low duty cycle that defines intervals during which the antenna is sampled for presence of the RF signals (e.g., approximately 20 ns every 100 &mgr;s).

Abstract: The present invention provides an RF tag having an antenna that can be selectively tuned to achieve optimal performance. The RF tag comprises an RF transponder integrated circuit and an antenna connected to the RF transponder integrated circuit. The antenna includes components such as tuning stubs and loading bars that are physically alterable to selectively vary the performance characteristics of the antenna. The tuning stub and loading bar may each further comprising a variably selectable length having elements that may be removed by punching, cutting, etching, laser trimming or other process. The antenna may further comprise a leadframe or a flexible substrate.

Abstract: A Write Broadcast system and method uses a base station to write sent data to all or some selected number (sub group) of tags in a base station field simultaneously. By unselecting the tags that have been successfully written to, and requesting a response from the remaining tags in the field (or sub group), the system determines, by receiving a response to the request, that there are tags in the field (sub group) that were unsuccessfully written to. Another Write Broadcast signal is sent to these tags. The system is useful for quickly (simultaneously) “stamping” information on the tag memory of a large number of tags in the field of the base station.

Abstract: Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.

Abstract: A radio frequency identification (RFID) transponder (tag) integrated circuit includes “on-chip” test circuitry. The test circuitry includes a serially-loaded test register. The test register controls the execution of on-chip tests. Such tests may include the testing of EEPROM circuitry included within the IC, the testing of analog circuitry, or the testing of digital circuitry included within the IC.

Abstract: The present invention assures the integrity of state information retained by a Radio Frequency Transponder during a loss of power. During the regular operation of the Transponder power is provided to a voltage-storing device powering an information retention mechanism of the Transponder. After the loss and reestablishing of power to the Transponder but before the Transponder is restarted, the voltage-storing device is checked to determine whether sufficient power is present in the information retention mechanism to retain information without corruption. If sufficient power is present, a signal to indicate that fact is communicated to the Transponder and the stored information is restored. The Transponder is then restarted.

Abstract: An RFID tag's mobility can be increased and cost can be decreased by using high-performance mobile power antennas instead of battery powered tags. Disclosed are some power antennas that include a half wave rectifier, a full wave rectifier, and a voltage multiplier. These antennas can be cascaded to boost the power or voltage gain. Additionally, planar elements can be added to increase efficiency without decreasing mobility.