Abstract: Methods for controlling catalysis of a chemical reaction generally includes electrostatically controlling position of a first linear single-molecule polymer inside at least one nanopore fluidly coupled to a reaction chamber comprising a reaction medium and at least one reactant, wherein the first linear single-molecule polymer is coupled to a first catalyst at one end and includes one or more charged sub-units; and creating an electrostatic potential well inside the nanopore, wherein the electrostatic potential well controls a position of the first linear single-molecule polymer inside the at least one nanopore. Also disclosed are apparatuses for controlling catalysis of the chemical reaction.

Abstract: An RFID tag's mobility can be increased and cost can be decreased by using high-performance mobile power antennas instead of battery powered tags. Disclosed are some power antennas that include a half wave rectifier, a full wave rectifier, and a voltage multiplier. These antennas can be cascaded to boost the power or voltage gain. Additionally, planar elements can be added to increase efficiency without decreasing mobility.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.

Abstract: In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

Abstract: A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.

Abstract: Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.

Abstract: Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

Abstract: Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

Abstract: A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.

Abstract: A system and method are provided for modifying the effective reading range of an radio frequency identification tag. The tag, a chip based tag, includes an antenna and a chip in communication with the antenna. The chip includes circuitry including field effect transistors that can modify the effective reading range of the tag by modifying characteristics of the tag including the modulation depth of the backscatter signal, the impedance characteristics of the tag front end electronics, the power consumption characteristics and the threshold power-on voltage of the tag. These characteristics are change either temporarily or permanently in response to commands communicated to the tag from a radio frequency identification reader.

Abstract: A system and method are provided for modifying the effective reading range of an radio frequency identification tag. The tag, a chip-based tag, includes an antenna and a chip in communication with the antenna. The chip includes circuitry including field effect transistors that can modify the effective reading range of the tag by modifying characteristics of the tag including the modulation depth of the backscatter signal, the impedance characteristics of the tag front end electronics, the power consumption characteristics and the threshold power-on voltage of the tag. These characteristics are change either temporarily or permanently in response to commands communicated to the tag from a radio frequency identification reader.

Abstract: PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.

Abstract: A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.

Abstract: Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

Abstract: A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.

Abstract: A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.