Patents by Inventor Daniele Balluchi

Daniele Balluchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250245098
    Abstract: A media management operation is initiated on a plurality of management units of one or more memory devices managed by the controller. A first error status and second error status associated with a read stage of the media management operation performed on a first management unit of the plurality of management units is received. An error correction operation on the first management unit is performed responsive to determining that the first error status and the second error status indicate a correctable error in the first management unit. An entry mapping a logical address to a physical address associated with the first management unit is locked responsive to determining that no spare management unit is available.
    Type: Application
    Filed: January 16, 2025
    Publication date: July 31, 2025
    Inventors: Emanuele Confalonieri, Marco Sforzin, Daniele Balluchi, Danilo Caraccio, Ravi Kiran Gummaluri, Stephen Scott Pawlowski
  • Patent number: 12366996
    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
    Type: Grant
    Filed: April 8, 2024
    Date of Patent: July 22, 2025
    Inventors: Victor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren
  • Publication number: 20250208950
    Abstract: The present disclosure includes apparatuses, methods, and systems for memory maintenance operations. An embodiment includes a memory having a plurality of groups of memory cells, wherein one of the plurality of groups of memory cells does not have data stored therein and all other ones of the plurality of groups of memory cells have data stored therein, and a controller coupled to the memory and having circuitry configured to determine one of the plurality of groups of memory cells that has data stored therein is a bad group of memory cells, recover the data stored in the bad group of memory cells, program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, and retire the bad group of memory cells.
    Type: Application
    Filed: July 31, 2024
    Publication date: June 26, 2025
    Inventors: Daniele Balluchi, Marco Sforzin, Paolo Amato
  • Patent number: 12315580
    Abstract: Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 27, 2025
    Assignee: Micron Technology, Inc.
    Inventors: William Yu, Daniele Balluchi, Danilo Caraccio, Thomas T. Tangelder, Jacob S. Robertson, James G. Steele, Joemar Sinipete
  • Publication number: 20250156272
    Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Inventors: Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri, Marco Sforzin
  • Patent number: 12293803
    Abstract: Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: William Yu, Daniele Balluchi, Chad B. Erickson, Danilo Caraccio
  • Publication number: 20250094344
    Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: July 24, 2024
    Publication date: March 20, 2025
    Inventors: Rishabh Dubey, Marco Sforzin, Emanuele Confalonieri, Danilo Caraccio, Daniele Balluchi, Nicola Del Gatto
  • Publication number: 20250094343
    Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: July 24, 2024
    Publication date: March 20, 2025
    Inventors: Rishabh Dubey, Marco Sforzin, Emanuele Confalonieri, Danilo Caraccio, Daniele Balluchi, Nicola Del Gatto
  • Publication number: 20250094278
    Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.
    Type: Application
    Filed: July 19, 2024
    Publication date: March 20, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Marco SFORZIN, Emanuele CONFALONIERI, Daniele BALLUCHI, Danilo CARACCIO, Nicola DEL GATTO, Rishabh DUBEY
  • Publication number: 20250094047
    Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: July 24, 2024
    Publication date: March 20, 2025
    Inventors: Marco Sforzin, Rishabh Dubey, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri, Nicola Del Gatto
  • Publication number: 20250077348
    Abstract: A variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. The one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. Arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. Other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. Combinations of arrangements may be implemented. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: July 18, 2024
    Publication date: March 6, 2025
    Inventors: Antonino Capri', Daniele Balluchi, Joseph M. McCrate, Graziano Mirichigni, Danilo Caraccio, Marco Sforzin
  • Publication number: 20250069680
    Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Inventors: Danilo Caraccio, Antonino Caprì, Daniele Balluchi, Massimiliano Patriarca
  • Patent number: 12235722
    Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri, Marco Sforzin
  • Publication number: 20250053343
    Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Amitava Majumdar, Anandhavel Nagendrakumar, Mohammed Ebrahim Hargan, Scott Garner, Danilo Caraccio, Daniele Balluchi, Chia Wei Chang, Ankush Lal
  • Publication number: 20250053222
    Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Greg Blodgett, Daniele Balluchi, Danilo Caraccio, Graziano Mirichigni
  • Publication number: 20250028486
    Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.
    Type: Application
    Filed: August 13, 2024
    Publication date: January 23, 2025
    Inventors: Danilo Caraccio, Paolo Amato, Daniele Balluchi
  • Publication number: 20250021262
    Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.
    Type: Application
    Filed: October 2, 2024
    Publication date: January 16, 2025
    Inventors: Marco Sforzin, Daniele Balluchi
  • Publication number: 20250014629
    Abstract: A method including obtaining temperature values of a region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of the region of the non-volatile memory, summing subsequent computed values of the operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on the comparison, performing a management operation on the cells of the region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Inventors: Dionisio Minopoli, Marco Sforzin, Daniele Balluchi
  • Patent number: 12189478
    Abstract: A system and method for memory error recovery in compute express link (CXL) components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 7, 2025
    Inventors: Marco Sforzin, Paolo Amato, Daniele Balluchi
  • Publication number: 20240411451
    Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.
    Type: Application
    Filed: August 19, 2024
    Publication date: December 12, 2024
    Inventors: Marco Sforzin, Paolo Amato, Daniele Balluchi